Lattice Semiconductor
ispXPLD 5000MX Family Data Sheet
ispXPLD 5000MX Family Internal Switching Characteristics
Over Recommended Operating Conditions
Parameter
Description
Base
Parameter
In/Out Delays
tIN
Input Buffer Delay
—
tGCLK_IN
Global Clock Input
Buffer Delay
—
tRST
Global RESET Pin
Delay
—
tGOE
Global OE Pin
Delay
—
tBUF
Delay through
Output Buffer
—
tEN
Output Enable Time
—
tDIS
Output Disable
Time
—
Routing Delays
tROUTE
tINREG
Delay through SRP
—
Input Buffer to
Macrocell Register
—
Delay
tPTSA
Product Term
Sharing Array Delay
—
tFBK
Internal Feedback
Delay
—
tGCLK
Global Clock Tree
Delay
—
tBCLK
Block PT Clock
Delay
—
tPTCLK
Macrocell PT Clock
Delay
—
tPLL_DELAY
Programmable PLL
Delay Increment
—
tBSR
Block PT Reset
Delay
—
tPTSR
Macrocell PT Set/
Reset Delay
—
tLPTOE
Macrocell PT OE
Delay
—
tSPTOE
Segment PT OE
Delay
—
tOSA
Output Sharing
Array Delay
—
tPTOE
tPDB
Global PT OE Delay
—
5-PT Bypass
Propagation Delay
—
tPDI
Macrocell
Propagation Delay
—
-4
-45
-5
-52
-75
Min. Max. Min. Max. Min. Max. Min. Max. Min. Max. Units
— 0.70 — 0.91 — 0.96 — 1.11 — 1.30 ns
— 0.40 — 0.35 — 0.35 — 0.35 — 0.55 ns
— 3.77 — 4.24 — 4.71 — 4.71 — 7.07 ns
— 1.98 — 2.66 — 2.34 — 2.87 — 3.27 ns
— 1.16 — 1.30 — 1.45 — 1.60 — 2.17 ns
— 2.52 — 2.84 — 3.16 — 3.63 — 4.23 ns
— 1.92 — 2.40 — 2.40 — 2.40 — 3.60 ns
— 1.95 — 2.06 — 2.34 — 2.24 — 3.66 ns
— 0.60 — 0.60 — 0.60 — 0.47 — 1.63 ns
— 0.50 — 0.50 — 0.53 — 0.83 — 1.34 ns
— 0.19 — 0.02 — 0.39 — 0.03 — 0.60 ns
— 0.52 — 0.32 — 0.72 — 0.82 — 0.78 ns
— 0.12 — 0.14 — 0.15 — 0.15 — 0.23 ns
— 0.12 — 0.14 — 0.15 — 0.15 — 0.23 ns
— 0.30 — 0.30 — 0.30 — 0.30 — 0.30 ns
— 0.72 — 0.81 — 0.90 — 0.94 — 1.35 ns
— 0.60 — 0.75 — 0.75 — 0.75 — 1.13 ns
— 0.83 — 1.19 — 1.04 — 1.52 — 1.31 ns
— 0.83 — 1.19 — 1.04 — 1.52 — 1.31 ns
— 0.80 — 0.90 — 1.00 — 1.00 — 1.50 ns
— 0.83 — 1.04 — 1.04 — 1.04 — 1.56 ns
— 0.20 — 0.23 — 0.25 — 0.25 — 0.38 ns
— 0.50 — 0.93 — 0.72 — 0.72 — 1.04 ns
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