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CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name
Description
MFG CO.
CL-PS7111-VC-A
Cirrus-Logic
Cirrus Logic 
CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
5.26 Clear All Start Up Reason Flags Location — STFCLR
A write to this location clears all the start-up reason flags in the System Flags Status register (SYSFLG).
5.27 Battery Low End-of-Interrupt — BLEOI
A write to this location clears the interrupt generated by a low battery (falling BATOK with NEXTPWR
high).
5.28 Media Changed End-of-Interrupt — MCEOI
A write to this location clears the interrupt generated by a rising edge of the NMEDCHG input pin.
5.29 Tick End-of-Interrupt Location — TEOI
A write to this location clears the current pending tick interrupt and watchdog interrupt.
5.30 End--of-Interrupt Location — TC1EOI TC1
A write to this location clears the under-flow interrupt generated by TC1.
5.31 End-of-Interrupt Location — TC2EOI TC2
A write to this location clears the under-flow interrupt generated by TC2.
5.32 RTC Match End-of-Interrupt — RTCEOI
A write to this location clears the RTC match interrupt.
5.33 UART1 Modem Status Changed End-of-Interrupt — UMSEOI
A write to this location clears the modem status changed interrupt.
5.34 Codec End-of-Interrupt Location — COEOI
A write to this location clears the sound interrupt (CSINT).
5.35 Enter Idle State Location — HALT
A write to this location places the system into the idle state by halting the clock to the processor until an
interrupt is generated. A write to this location while there is an active interrupt has no effect.
5.36 Enter Standby State Location — STDBY
A write to this location places the system into the standby state by halting the main oscillator. It automat-
ically switches the DRAMs to self-refresh if the RFSHEN bit is set in the DRAM Refresh Period register.
All transitions to the standby state are synchronized with DRAM cycles. A write to this location while there
is an active interrupt has no effect.
September 1997
PRELIMINARY DATA BOOK v2.0
69
REGISTER DESCRIPTIONS

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