CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

5.20 Codec Interface Data Register — CODR

The CODR register is a 16-bit read/write register, which is used with the codec interface when this is

selected by the appropriate setting of SYSCON2[0] (SERSEL). Data written to or read from this register

is pushed or popped onto the appropriate 16-byte FIFO buffer. Data from this buffer is then serialized and

sent to or received from the codec sound device. When the CODEC is enabled, the codec interrupt CSINT

is generated repetitively at 1/8th of the byte transfer rate and the state of the FIFOs can be read in the

System Flags register. The net data transfer rate to/from the codec device is 8 Kbytes per second giving

an interrupt rate of 1 kHz.

5.21 UART Data Registers — UARTDR1–2

10

OVERR

9

PARERR

8

FRMERR

7:0

Rx data

The UARTDR registers are an 11-bit read and 8-bit write register for all data transfers to or from the inter-

nal UARTs 1 and 2.

Data written to this register is pushed onto the 16-byte data Tx holding FIFO if the FIFO is enabled; if not,

it is stored in a 1-byte holding register. This write initiates transmission from the UART.

The UART Data Read register comprises the 8-bit data byte received from the UART together with three

bits of error status. Data read from this register is popped from the 16-byte data Rx FIFO if the FIFO is

enabled, if not it is read from a 1-byte buffer register containing the last byte received by the UART. Data

received and error status is automatically pushed onto the Rx FIFO if it is enabled. The Rx FIFO is 10 bits

wide by 16 deep.

Bit Description

10 PARERR: UART parity error. This bit is set if the UART detected a parity error while receiving the data byte.

9 OVERR: UART overrun error. This bit is set if more data is received by the UART and the FIFO is full. The Overrun

Error bit is not associated with any single character and so is not stored in the FIFO, if this bit is set, the entire contents

of the FIFO is invalid and should be cleared. This error bit is cleared by reading the UARTDR register.

8 FRMERR: UART framing error. This bit is set if the UART detected a framing error while receiving the associated data

byte. Framing errors are caused by non-matching word lengths or bit rates.

7:0 Rx Data: This 8-bit field contains the receive data.

64

REGISTER DESCRIPTIONS

September 1997

PRELIMINARY DATA BOOK v2.0

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