CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

Bit Description (cont.)

11:0 Bit Rate Divisor: This 12-bit field set the bit rate. If the system is operating with an 18.432-MHz master clock, then the

bit rate divider is fed by a clock frequency of 3.6864 MHz, which is then further divided internally by 16 to give the bit

rate. The formula to give the divisor value for any bit rate when operating from the 18.432-MHz clock is:

Divisor = (230400 ÷ bit rate) − 1

Equation 5-9

A value of ‘0’ in this field is illegal when in the 18.432-MHz mode. In 13-MHz mode, the clock frequency fed to the

UART is 1.8571 MHz. In this mode, ‘0’ is a legal divisor value and generates the maximum possible bit rate. The follow-

ing tables show example bit rates with the corresponding divisor value.

Table 5-3. UART Bit Rates at

18.432-MHz Clock Rate

Table 5-4. UART Bit Rates at 13-MHz

Clock Rate

Divisor

Value

Bit Rate at

18.432 MHz

Divisor Bit Rate

Error on

Value at 13 MHz 13-MHz value

0

—

1

115200

2

76800

3

57600

5

38400

11

19200

15

14400

23

9600

95

2400

191

1200

0

1

2

5

7

11

47

96

1054

116071

58036

38690

19345

14509

9673

2418

1196

110.02

0.75%

0.75%

0.75%

0.75%

0.75%

0.75%

0.42%

0.28%

0.18%

2094

110

66

REGISTER DESCRIPTIONS

September 1997

PRELIMINARY DATA BOOK v2.0

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