CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

5.19 Pump Control Register — PMPCON

11:8

Drive 1 pump ratio

7:4

Drive 0 from mains ratio

3:0

Drive 0 from battery ratio

The DC-to-DC Converter Pump Control register is a 12-bit read/write-only register that sets and controls

the variable mark space ratio drives for two DC-to-DC converters. All bits in this register are cleared by a

system reset.

Bit Description

Drive 0 from Battery: This 4-bit field controls the on time for the drive 0 DC-to-DC pump while the system is pow-

ered from batteries. Setting these bits to ‘0’ disables this pump, setting these bits to ‘1’ allows the pump to be

3:0 driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc., up to a 15:16 duty ratio. An 8:16 duty ratio results in a square

wave of 96 kHz when operating with an 18.432-MHz master clock, or 101.6 kHz when operating from the 13-MHz

source. The NEXTPWR input is used to switch between the two on times for ‘drive0’.

Drive 0 from Mains: This 4-bit field controls the on time for the drive 0 DC-to-DC pump while the system is pow-

ered from mains. Setting these bits to ‘0’ disables this pump; setting these bits to ‘1’ allows the pump to be driven

7:4 in a 1:16 duty ratio, 2 in a 2:16 duty ratio, etc., up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave

of 96 kHz when operating with an 18.432-MHz master clock, or 101.6 kHz when operating from the 13-MHz

source. The NEXTPWR input switches between the two on times for ‘drive 0’.

Drive 1 Pump Ratio: This 4-bit field controls the on time for the drive 1 DC-to-DC pump. Setting these bits to ‘0’

disables this pump, setting these bits to ‘1’ allows the pump to be driven in a 1:16 duty ratio, 2 in a 2:16 duty ratio,

etc., up to a 15:16 duty ratio. An 8:16 duty ratio results in a square wave of 96 kHz when operating with an

18.432-MHz master clock, or 101.6 kHz when operating from the 13-MHz source.

The state of the output drive pins is latched during power-on reset, this latched value is used to determine the

polarity of the drive output. The sense of the DC-to-DC converter control lines is summarized in the following table.

11:8

Initial State of Drive ‘n’ during

POR

Sense of Drive ‘n’

Polarity of Bias Voltage

Low

High

Active high

+VE

Active low

-VE

September 1997

PRELIMINARY DATA BOOK v2.0

63

REGISTER DESCRIPTIONS

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