CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CL-PS7111-VC-A Datasheet PDF : 105 Pages
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CL-PS7111
Low-Power System-on-a-Chip
5.11 DRAM Refresh Period Register — DRFPR
7
6
5
4
3
2
1
0
RFSHEN
RFDIV
The DRAM Refresh Period register is an 8-bit read/write register that enables refresh and selects the
refresh period used by the DRAM controller for its periodic CAS-before-RAS refresh. The value in the
DRAM refresh period register is only cleared by a power on reset, that is, the register state is maintained
during a power fail or user reset.
Bit Description
7 RFSHEN: DRAM refresh enable. Setting this bit enables periodic refresh cycles to be generated by the CL-PS7111 at
a rate set by the RFDIV field. Setting this bit also enables Self-refresh mode when the CL-PS7111 is in the standby
state.
6:0 RFDIV: This 7-bit field sets the DRAM refresh rate. The refresh period is derived from a 128-kHz clock as shown in
Equation 5-1.
Frequency (kHz) = 128/(RFDIV + 1), that is,
RFDIV = (128/Refresh frequency (kHz)) − 1
Equation 5-1
This equation is valid for both 13-MHz and 18-MHz modes. The equation for frequency gives the refresh rate for the
DRAM.
The maximum refresh frequency is 64 kHz, the minimum is 1 kHz. The RFDIV field should not be programmed with ‘0’
as this results in no refresh cycles being initiated. These values are valid for both 13-MHz and 18-MHz modes of oper-
ation.
September 1997
PRELIMINARY DATA BOOK v2.0
57
REGISTER DESCRIPTIONS
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