CL-PS7111-VC-A View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CL-PS7111-VC-A

Low-Power System-on-a-Chip

Cirrus Logic 

CL-PS7111

Low-Power System-on-a-Chip

Bit Description (cont.)

28:27 BOOTBIT0–1: These bits indicate the default (power-on reset) bus width of the ROM interface. See the Memory Con-

figuration registers on page 53 for more details on the ROM interface bus width. The state of these bits reflects the

state of Port E bits 0–1 during power-on reset, as shown in the following table:

PE1 (BOOTBIT1) PE0 (BOOTBIT0)

0

0

0

1

1

0

1

1

Boot Option

32 bit

8 bit

16 bit

Reserved

26 SSIBUSY: Synchronous serial interface busy. This bit is set while data is shofted in or out of the seynchronous serial

interface. When this bit is clear, data is valid for reads.

25 CTXFF: Codec Tx FIFO full bit. This is set if the 16-byte codec Tx FIFO is full.

24 CRXFE: Codec Rx FIFO empty bit. This is set if the 16-byte codec Rx FIFO is empty.

23 UTXFF1: UART1 transmit FIFO full. The meaning of this bit depends on the state of the UFIFOEN bit in the UART1 Bit

Rate and Line Control register. If the FIFO is disabled, this bit is set when the Tx Holding register is full. If the FIFO is

enabled, the UTXFF1 bit is set when the Tx FIFO is full.

22 URXFE1: UART1 receiver FIFO empty. The meaning of this bit depends on the state of the UFIFOEN bit in the UART1

Bit Rate and Line Control register. If the FIFO is disabled, this bit is set when the Rx Holding register is empty. If the

FIFO is enabled the URXFE bit is set when the Rx FIFO is empty.

21:16 RTCDIV: This 6-bit field reflects the number of 64-Hz ticks that have passed since the last increment of the RTC. It is

the output of the divide-by-64 chain that divides the 64-Hz tick clock down to 1 Hz for the RTC. The MSB is the 32-Hz

output; the LSB is the 1-Hz output.

15 CLDFLG: Cold start flag. This bit is set if the CL-PS7111 has been reset with a power on reset; it is cleared by writing

to the STFCLR location.

14 PFFLG: Power fail flag. This bit is set if the system has been reset by the power fail input pin, it is cleared by writing to

the STFCLR location.

13 RSTFLG: Reset flag. This bit is set if the RESET button is pressed, forcing the NURESET input low. It is cleared by

writing to the STFCLR location.

12 NBFLG: New battery flag. This bit is set if a low-to-high transition has occurred on the NBATCHG input; it is cleared by

writing to the STFCLR location.

11 UBUSY1: UART1 transmitter busy. This bit is set while the UART1 is busy transmitting data; it is guaranteed to remain

set until the complete byte has been sent, including all stop bits.

10 DCD: This bit reflects the current status of the data carrier detect (DCD) modem-control input to the UART1.

9 DSR: This bit reflects the current status of the data set ready (DSR) modem-control input to the UART1.

8 CTS: This bit reflects the current status of the clear to send (CTS) modem-control input to the UART1.

September 1997

PRELIMINARY DATA BOOK v2.0

51

REGISTER DESCRIPTIONS

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