CS5345(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5345
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

6.3.1 Functional Mode (Bits 7:6)

Function:

Selects the required range of sample rates.

Table 5. Functional Mode Selection

FM1

0

0

1

1

FM0

0

1

0

1

Mode

Single-Speed Mode: 4 to 50 kHz sample rates

Double-Speed Mode: 50 to 100 kHz sample rates

Quad-Speed Mode: 100 to 200 kHz sample rates

Reserved

6.3.2 Digital Interface Format (Bit 4)

Function:

The required relationship between LRCK, SCLK and SDOUT is defined by the Digital Interface For-

mat bit. The options are detailed in Table 6 and may be seen in Figure 3 and 4.

Table 6. Digital Interface Formats

6.3.3

DIF

Description

0

Left Justified, up to 24-bit data (default)

1

I2S, up to 24-bit data

Mute (Bit 2)

Format

0

1

Figure

3

4

Function:

When this bit is set, the serial audio output of the both channels will be muted.

6.3.4 High Pass Filter Freeze (Bit 1)

Function:

When this bit is set, the internal high-pass filter will be disabled.The current DC offset value will be

frozen and continue to be subtracted from the conversion result. See “High Pass Filter and DC Offset

Calibration” on page 22.

6.3.5 Master / Slave Mode (Bit 0)

Function:

This bit selects either master or slave operation for the serial audio port. Setting this bit will select mas-

ter mode, while clearing this bit will select slave mode.

6.4 MCLK Frequency - Address 05h

7

Reserved

6

MCLK

Freq2

5

MCLK

Freq1

4

MCLK

Freq0

3

Reserved

2

Reserved

1

Reserved

0

Reserved

30

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