CS5345(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5345
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

The CS5345 includes an auxiliary analog output through the PGAOUT pins. These pins can be configured to output

the analog input to the ADC as selected by the input MUX and gained or attenuated with the PGA, or alternatively,

they may be set to high-impedance. See the “PGAOut Source Select (Bit 6)” section on page 31 for information on

configuring the PGA auxiliary analog output.

The PGA auxiliary analog output can source very little current. As current from the PGAOUT pins increases, distor-

tion will increase. For this reason, a high input impedance buffer must be used on the PGAOUT pins to achieve full

performance. Refer to the PGAOUT Analog Characteristics table on page 12 for acceptable loading conditions.

4.7 Control Port Description and Timing

The control port is used to access the registers, allowing the CS5345 to be configured for the desired operational

modes and formats. The operation of the control port may be completely asynchronous with respect to the audio

sample rates. However, to avoid potential interference problems, the control port pins should remain static if no op-

eration is required.

The control port has 2 modes: SPI and I²C, with the CS5345 acting as a slave device. SPI mode is selected if there

is a high to low transition on the AD0/CS pin, after the RESET pin has been brought high. I²C mode is selected by

connecting the AD0/CS pin through a resistor to VLC or DGND, thereby permanently selecting the desired AD0 bit

address state.

4.7.1 SPI Mode

In SPI mode, CS is the CS5345 chip select signal, CCLK is the control port bit clock (input into the CS5345 from the

microcontroller), CDIN is the input data line from the microcontroller, CDOUT is the output data line to the microcon-

troller. Data is clocked in on the rising edge of CCLK and out on the falling edge.

Figure 10 shows the operation of the control port in SPI mode. To write to a register, bring CS low. The first seven

bits on CDIN form the chip address and must be 1001111. The eighth bit is a read/write indicator (R/W), which

should be low to write. The next eight bits form the Memory Address Pointer (MAP), which is set to the address of

the register that is to be updated. The next eight bits are the data which will be placed into the register designated

by the MAP. During writes, the CDOUT output stays in the Hi-Z state. It may be externally pulled high or low with a

47 kΩ resistor, if desired.

There is a MAP auto increment capability, enabled by the INCR bit in the MAP register. If INCR is a zero, the MAP

will stay constant for successive read or writes. If INCR is set to a 1, the MAP will auto-increment after each byte is

read or written, allowing block reads or writes of successive registers.

To read a register, the MAP has to be set to the correct address by executing a partial write cycle which finishes (CS

high) immediately after the MAP byte. The MAP auto increment bit (INCR) may be set or not, as desired. To begin

a read, bring CS low, send out the chip address and set the read/write bit (R/W) high. The next falling edge of CCLK

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