CS5345(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5345
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

SCL

SDA

0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28

CHIP ADDRESS (WRITE)

MAP BYTE

STOP

CHIP ADDRESS (READ)

DATA

DATA +1 DATA + n

1 0 0 1 1 AD1 AD0 0

INCR 6 5 4 3 2 1 0

1 0 0 1 1 AD1 AD0 1

70

7

0

7

0

START

ACK

ACK

START

ACK

ACK

NO

ACK STOP

Figure 12. Control Port Timing, I²C Read

Since the read operation can not set the MAP, an aborted write operation is used as a preamble. As shown in

Figure 12, the write operation is aborted after the acknowledge for the MAP byte by sending a stop condition. The

following pseudocode illustrates an aborted write operation followed by a read operation.

Send start condition.

Send 10011xx0 (chip address & write operation).

Receive acknowledge bit.

Send MAP byte, auto increment off.

Receive acknowledge bit.

Send stop condition, aborting write.

Send start condition.

Send 10011xx1(chip address & read operation).

Receive acknowledge bit.

Receive byte, contents of selected register.

Send acknowledge bit.

Send stop condition.

Setting the auto increment bit in the MAP allows successive reads or writes of consecutive registers. Each

byte is separated by an acknowledge bit.

26

Share Link: