CS5345(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5345
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

4.8 Interrupts and Overflow

The CS5345 has a comprehensive interrupt capability. The INT output pin is intended to drive the interrupt input pin

on the host microcontroller. The INT pin may function as either an active high CMOS driver or an active low open-

drain driver (see “Active High/Low (Bit 0)” on page 33). When configured as active low open-drain, the INT pin has

no active pull-up transistor, allowing it to be used for wired-OR hook-ups with multiple peripherals connected to the

microcontroller interrupt input pin. In this configuration, an external pull-up resistor must be placed on the INT pin for

proper operation.

Many conditions can cause an interrupt, as listed in the interrupt status register descriptions. See “Interrupt Status

- Address 0Dh” on page 33. Each source may be masked off through mask register bits. In addition, each source

may be set to rising edge, falling edge, or level sensitive. Combined with the option of level sensitive or edge sensi-

tive modes within the microcontroller, many different configurations are possible, depending on the needs of the

equipment designer.

The CS5345 also has a dedicated overflow output. The OVFL pin functions as active low open drain and has no

active pull-up transistor, thereby requiring an external pull-up resistor. The OVFL pin outputs an OR of the ADCOv-

erflow and ADCUnderflow conditions available in the Interrupt Status register, however, these conditions do not

need to be unmasked for proper operation of the OVFL pin.

4.9 Reset

When RESET is low, the CS5345 enters a low power mode and all internal states are reset, including the control

port and registers, and the outputs are muted. When RESET is high, the control port becomes operational and the

desired settings should be loaded into the control registers. Writing a 0 to the PDN bit in the Power Control register

will then cause the part to leave the low power state and begin operation.

The delta-sigma modulators settle in a matter of microseconds after the analog section is powered, either through

the application of power or by setting the RESET pin high. However, the voltage reference will take much longer to

reach a final value due to the presence of external capacitance on the FILT+ pin. During this voltage reference ramp

delay, SDOUT will be automatically muted.

It is recommended that RESET be activated if the analog or digital supplies drop below the recommended operating

condition to prevent power glitch related issues.

4.10 Synchronization of Multiple Devices

In systems where multiple ADCs are required, care must be taken to achieve simultaneous sampling. To ensure

synchronous sampling, the master clocks and left/right clocks must be the same for all of the CS5345’s in the sys-

tem. If only one master clock source is needed, one solution is to place one CS5345 in Master Mode, and slave all

of the other CS5345’s to the one master. If multiple master clock sources are needed, a possible solution would be

to supply all clocks from the same external source and time the CS5345 reset with the inactive edge of master clock.

This will ensure that all converters begin sampling on the same clock edge.

4.11 Grounding and Power Supply Decoupling

As with any high resolution converter, the CS5345 requires careful attention to power supply and grounding arrange-

ments if its potential performance is to be realized. Figure 7 shows the recommended power arrangements, with VA

connected to a clean supply. VD, which powers the digital filter, may be run from the system logic supply (VLS or

VLC) or may be powered from the analog supply (VA) via a resistor. In this case, no additional devices should be

powered from VD. Power supply decoupling capacitors should be as near to the CS5345 as possible, with the low

value ceramic capacitor being the nearest. All signals, especially clocks, should be kept away from the FILT+ and

VQ pins in order to avoid unwanted coupling into the modulators. The FILT+ and VQ decoupling capacitors, partic-

ularly the 0.1 µF, must be positioned to minimize the electrical path from FILT+ and AGND. The CS5345 evaluation

board demonstrates the optimum layout and power supply arrangements. To minimize digital noise, connect the

CS5345 digital outputs only to CMOS inputs.

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