CS5345(2004) View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5345
(Rev.:2004)

105 dB, 24-Bit, 192 kHz Stereo Audio ADC

Cirrus Logic 

CS5345

The high pass filter continuously subtracts a measure of the DC offset from the output of the decimation filter. If the

HPFFreeze bit (see page 30) is set during normal operation, the current value of the DC offset for the each channel

is frozen and this DC offset will continue to be subtracted from the conversion result. This feature makes it possible

to perform a system DC offset calibration by:

1) Running the CS5345 with the high pass filter enabled until the filter settles. See the Digital Filter Characteristics

section for filter settling time.

2) Disabling the high pass filter and freezing the stored DC offset.

A system calibration performed in this way will eliminate offsets anywhere in the signal path between the calibration

point and the CS5345.

4.4 Analog Input Multiplexer, PGA, and Mic Gain

The CS5345 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier (PGA).

The input multiplexer can select one of 6 possible stereo analog input sources and route it to the PGA.

Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing them to be

used for microphone level signals without the need for any external gain. The PGA stage provides ±12 dB of gain

or attenuation in 0.5 dB steps. Figure 9 shows the architecture of the input multiplexer, PGA, and mic gain stages.

AIN1A

AIN2A

AIN3A

AIN4A/MICIN1

AIN5A

AIN6A

AIN1B

AIN2B

AIN3B

AIN4B/MICIN2

AIN5B

AIN6B

+32 dB

+32 dB

MUX

PGA

Channel A

PGA Gain Bits

Analog Input

Selection Bits

Channel B

PGA Gain Bits

MUX

PGA

Out to ADC

Channel A

Out to ADC

Channel B

Figure 9. Analog Input Architecture

The “Analog Input Selection (Bits 2:0)” section on page 33 outlines the bit settings necessary to control the input

multiplexer and mic gain. “Channel A PGA Control - Address 07h” on page 31 and “Channel B PGA Control - Ad-

dress 08h” on page 31 outlines the register settings necessary to control the PGA. By default, line level input 1 is

selected, and the PGA is set to 0 dB.

4.5 Input Connections

The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject signals with-

in the stopband of the filter. However, there is no rejection for input signals which are (n × 6.144 MHz) the digital

passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram for the recommended analog input

circuit that will attenuate noise energy at 6.144 MHz. The use of capacitors which have a large voltage coefficient

(such as general purpose ceramics) must be avoided since these can degrade signal linearity. Any unused analog

input pairs should be left unconnected.

4.6 PGA Auxiliary Analog Output

23

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