C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 15.5. XBR2: Port I/O CrossBar Register 2

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

WEAKPUD XBARE

-

-

-

-

-

CNVSTE 00000000

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xE3

Bit7: WEAKPUD: Port I/O Weak Pull-up Disable Bit

0: Weak Pull-ups Enabled (except for Ports whose I/O are configured as push-pull)

1: Weak Pull-ups Disabled

Bit6: XBARE: Crossbar Enable Bit

0: Crossbar Disabled

1: Crossbar Enabled

Bits5-1: UNUSED. Read = 00000b, Write = don’t care.

Bit0: CNVSTE: ADC Convert Start Input Enable Bit

0: CNVSTR unavailable at Port pin.

1: CNVSTR routed to Port Pin.

Example Usage of XBR0, XBR1, XBR2:

When selected, the digital resources fill the Port I/O pins in order (top to bottom as shown in

Table 15.1) starting with P0.0 through P0.7, and then P1.0 through P1.7, and finally P2.0

through P2.7. If the digital resources are not mapped to the Port I/O pins, they default to their

matching internal Port Register bits.

Example1: If XBR0 = 0x11, XBR1 = 0x00, and XBR2 = 0x40:

P0.0=SDA, P0.1=SCL, P0.2=CEX0, P0.3=CEX1, P0.4 … P2.7 map to corresponding Port I/O.

Example2: If XBR0 = 0x80, XBR1 = 0x04, and XBR2 = 0x41:

P0.0=CP0, P0.1=/INT0, P0.2 = CNVSTR, P0.3 … P2.7 map to corresponding Port I/O.

Rev. 1.7

108

Share Link: