C8051F007 View Datasheet(PDF) - Silicon Laboratories
Part Name
Description
MFG CO.
C8051F007 Datasheet PDF : 171 Pages
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C8051F000/1/2/5/6/7
C8051F010/1/2/5/6/7
not affect the push-pull Port I/O. Furthermore, the weak pullup is turned off on an open-drain output that is driving
a 0 to avoid unnecessary power dissipation.
The third and final step is to initialize the individual resources selected using the appropriate setup registers.
Initialization procedures for the various digital resources may be found in the detailed explanation of each available
function. The reset state of each register is shown in the figures that describe each individual register.
Figure 15.1. Port I/O Functional Block Diagram
Highest
Priority
Lowest
Priority
2
SMBus
4
SPI
2
UART
6
PCA
Comptr.
2
Outputs
T0, T1, T2,
T2EX,
/INT0,
6
/INT1
/SYSCLK
CNVSTR
XBR0, XBR1,
XBR2 Registers
PRT0CF, PRT1CF,
PRT2CF Registers
Priority
Decoder
8
Digital
Crossbar
8
P0
I/O
Cells
P1
I/O
Cells
External
Pins
P0.0
P0.7
Highest
Priority
P1.0
P1.7
Port
Latches
8
P0 (P0.0-P0.7)
8
P1 (P1.0-P1.7)
8
P2 (P2.0-P2.7)
8
P3 (P3.0-P3.7)
8
P2
I/O
Cells
PRT3CF
Register
P3
I/O
Cells
P2.0
P2.7
Lowest
Priority
P3.0
P3.7
WEAKPUD
Figure 15.2. Port I/O Cell Block Diagram
PUSH-PULL
/PORT-OUTENABLE
PORT-OUTPUT
VDD
VDD
(WEAK)
PORT
PAD
PORT-INPUT
VDD
DGND
Rev. 1.7
104
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