C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 11.4. FLSCL: Flash Memory Timing Prescaler

R/W

R/W

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

FOSE

FRAE

-

-

FLASCL

10001111

Bit7

Bit6

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xB6

Bit7: FOSE: Flash One-Shot Timer Enable

0: Flash One-shot timer disabled.

1: Flash One-shot timer enabled

Bit6: FRAE: Flash Read Always Enable

0: Flash reads per one-shot timer

1: Flash always in read mode

Bits5-4: UNUSED. Read = 00b, Write = don’t care.

Bits3-0: FLASCL: Flash Memory Timing Prescaler.

This register specifies the prescaler value for a given system clock required to generate the

correct timing for Flash write/erase operations. If the prescaler is set to 1111b, Flash

write/erase operations are disabled.

0000: System Clock < 50kHz

0001: 50kHz ≤ System Clock < 100kHz

0010: 100kHz ≤ System Clock < 200kHz

0011: 200kHz ≤ System Clock < 400kHz

0100: 400kHz ≤ System Clock < 800kHz

0101: 800kHz ≤ System Clock < 1.6MHz

0110: 1.6MHz ≤ System Clock < 3.2MHz

0111: 3.2MHz ≤ System Clock < 6.4MHz

1000: 6.4MHz ≤ System Clock < 12.8MHz

1001: 12.8MHz ≤ System Clock < 25.6MHz

1010: 25.6MHz ≤ System Clock < 51.2MHz *

1011, 1100, 1101, 1110: Reserved Values

1111: Flash Memory Write/Erase Disabled

The prescaler value is the smallest value satisfying the following equation:

FLASCL > log2(System Clock / 50kHz)

* For test purposes. The C8051F000 family is not guaranteed for operation over 25MHz.

91

Rev. 1.7

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