C8051F007 View Datasheet(PDF) - Silicon Laboratories

Part Name

Description

MFG CO.

C8051F007

Mixed-Signal 32KB ISP FLASH MCU Family

Silicon Laboratories 

C8051F000/1/2/5/6/7

C8051F010/1/2/5/6/7

Figure 15.3. XBR0: Port I/O CrossBar Register 0

R/W

CP0OEN

Bit7

R/W

ECIE

Bit6

R/W

R/W

R/W

R/W

R/W

R/W

Reset Value

PCA0ME

UARTEN SPI0OEN SMB0OEN 00000000

Bit5

Bit4

Bit3

Bit2

Bit1

Bit0

SFR Address:

0xE1

Bit7: CP0OEN: Comparator 0 Output Enable Bit

0: CP0 unavailable at Port pin.

1: CP0 routed to Port Pin.

Bit6: ECIE: PCA0 Counter Input Enable Bit

0: ECI unavailable at Port pin.

1: ECI routed to Port Pin.

Bits3-5: PCA0ME: PCA Module I/O Enable Bits

000: All PCA I/O unavailable at Port pins.

001: CEX0 routed to Port Pin.

010: CEX0, CEX1 routed to 2 Port Pins.

011: CEX0, CEX1, CEX2 routed to 3 Port Pins.

100: CEX0, CEX1, CEX2, CEX3 routed to 4 Port Pins.

101: CEX0, CEX1, CEX2, CEX3, CEX4 routed to 5 Port Pins.

110: RESERVED

111: RESERVED

Bit2: UARTEN: UART I/O Enable Bit

0: UART I/O unavailable at Port pins.

1: RX, TX routed to 2 Port Pins.

Bit1: SPI0OEN: SPI Bus I/O Enable Bit

0: SPI I/O unavailable at Port pins.

1: MISO, MOSI, SCK, and NSS routed to 4 Port Pins.

Bit0: SMB0OEN: SMBus Bus I/O Enable Bit

0: SMBus I/O unavailable at P0.0, P0.1.

1: SDA routed to P0.0, SCL routed to P0.1.

Rev. 1.7

106

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