CS8900 查看數據表（PDF） - Cirrus Logic

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CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

5.7 Transmit Operation

5.7.1 Overview

Packet transmission occurs in two phases. In the

first phase, the host moves the Ethernet frame

into the CS8900’s buffer memory. The first phase

begins with the host issuing a Transmit Com-

mand. This informs the CS8900 that a frame is

to be transmitted and tells the chip when (i.e. af-

ter 5, 381, or 1021 bytes have been transferred or

after the full frame has been transferred to the

CS8900) and how the frame should be sent (i.e.

with or without CRC, with or without pad bits,

etc.). The host follows the Transmit Command

with the Transmit Length, indicating how much

buffer space is required. When buffer space is

available, the host writes the Ethernet frame into

the CS8900’s internal memory, using either

Memory or I/O space.

In the second phase of transmission, the CS8900

converts the frame into an Ethernet packet then

transmits it onto the network. The second phase

begins with the CS8900 transmitting the pream-

ble and Start-of-Frame delimiter as soon as the

proper number of bytes has been transferred into

its transmit buffer (5, 381, 1021 bytes or full

frame, depending on configuration). The pream-

ble and Start-of-Frame delimiter are followed by

the data transferred into the on-chip buffer by the

host (Destination Address, Source Address,

Length field and LLC data). If the frame is less

than 64 bytes, including CRC, the CS8900 adds

pad bits if configured to do so. Finally, the

CS8900 appends the proper 32-bit CRC value.

5.7.2 Transmit Configuration

After each reset, the CS8900 must be configured

for transmit operation. This can be done auto-

matically using an attached EEPROM, or by

writing configuration commands to the CS8900’s

internal registers (see Section 3.1). The items

that must be configured include which physical

interface to use and which transmit events cause

interrupts.

Configuring the Physical Interface: Configuring

the physical interface consists of determining

which Ethernet interface should be active

(10BASE-T or AUI), and enabling the transmit

logic for serial transmission. Configuring the

Physical Interface is accomplished via the

LineCTL register (Register 13) and is described

in Table 5.12.

Note that the CS8900 transmits in 10BASE-T

mode when no link pulses are being received

only if bit DisableLT is set in register Test Con-

trol (Register 19).

Register 13, LineCTL

Bit Bit Name

Operation

7 SerTxON When set, transmission enabled.

8 AUIonly W h e n s e t , AUI s e le c t e d ( ta ke s

precedence over AutoAUI/10BT). When

clear, 10BASE-T selected.

9 AutoAUI/ When set, automatic interface

10BT selection enabled.

B

Mod W hen s et, the modified backoff

BackoffE algorithm is used. When clear, the

standard backoff algorithm is used.

D

2-part When set, two-part deferral is disabled.

DefDis

Table 5.12. Physical Interface Configuration

Selecting which Events Cause Interrupts: The

TxCFG register (Register 7) and the BufCFG

register (Register B) are used to determine which

transmit events will cause interrupts to the host

processor. Tables 5.13 and 5.14 describe the in-

terrupt enable (iE) bits in these registers.

DS150PP2

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