CS8900 查看數據表（PDF） - Cirrus Logic

零件编号

产品描述 (功能)

生产厂家

CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

Register 7, TxCFG

Bit Bit Name

Operation

6 Loss-of- W h e n s e t , t he r e is a n int e rr up t

CRSiE whenever the CS8900 fails to detect

Carrier Sense after transmitting the

preamble (applies to the AUI only).

7 SQEerroriE W h e n s e t , t he r e is a n int e rr up t

whenever there is an SQE error.

8 TxOKiE W h e n s e t , t he r e is a n int e rr up t

whenever a frame is transmitted

successfully.

9 Out-of- W h e n s e t , t he r e is a n int e rr up t

windowiE whenever a late collision is detected.

A JabberiE W h e n s e t , t he r e is a n int e rr up t

whenever there is a jabber condition.

B AnycolliE W h e n s e t , t he r e is a n int e rr up t

whenever there is a collision.

F 16colliE W h e n s e t , t he r e is a n int e rr up t

whenever the CS8900 attempts to

transmit a single frame 16 times.

Table 5.13. Transmitting Interrupt

Configuration

Register B, BufCFG

Bit Bit Name

Operation

8 Rdy4TxiE W h e n s e t , t he r e is a n int e rr up t

whenever buffer space becomes

available for a transmit frame (used

with a Transmit Request).

9 TxUnder When set, there is an interrupt when

RuniE the CS8900 runs out of data after

transmit has started.

A

TxCol W h e n s e t , t he r e is a n int e rr up t

OvfloiE whenever the TxCol counter overflows.

Table 5.14. Tranmit Interrupt Configuration

5.7.3 Changing the Configuration

When the host configures these registers it does

not need to change them for subsequent packet

transmissions. If the host does choose to change

the TxCFG or BufCFG registers, it may do so at

any time. The effects of the change are noticed

immediately. That is, any changes in the Inter-

rupt Enable (iE) bits may affect the packet

currently being transmitted.

If the host chooses to change bits in the

LineCTL register after initialization, the Mod-

BackoffE bit and any receive related bit

(LoRxSquelch, SerRxON) may be changed at

any time. However, the Auto AUI/10BT and

AUIonly bits should not be changed while the

SerTxON bit is set. If any of these three bits are

to be changed, the host should first clear the

SerTxON bit (Register 13, LineCTL, Bit 7), and

then set it when the changes are complete.

5.7.4 Enabling CRC Generation and Padding

Whenever the host issues a Transmit Request

command, it must indicate whether or not the

Cyclic Redundancy Check (CRC) value should

be appended to the transmit frame, and whether

or not pad bits should be added (if needed). Ta-

ble 5.15 describes how to configure the CS8900

for CRC generating and padding.

Inhibit

CRC

(Bit C)

0

1

0

1

Register 9, TxCMD

TxPad

Dis

(Bit D)

Operation

0 Pad to 64 bytes if necessary (including

CRC).

0 Send a runt frame if specified length

less than 60 bytes.

1 Pad to 60 bytes if necessary (without

CRC).

1 Send runt if specified length less than

64. The CS8900 will not transmit a

frame that is less than 3 bytes.

Table 5.15. CRC and Padding Configuration

5.7.5 Individual Packet Transmission

Whenever the host has a packet to transmit, it

must issue a Transmit Request to the CS8900

consisting of the following three operations in

the exact order shown:

1. The host must write a Transmit Command to

the TxCMD register (PacketPage base +

0144h). The contents of the TxCMD register

100

DS150PP2

Share Link: