CS8900 查看數據表（PDF） - Cirrus Logic

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CS8900

Highly-Integrated ISA Ethernet Controller

Cirrus Logic 

CS8900

A committed DMAed receive frame is freed

from commitment by any one of the following

conditions:

1. The host re-reads the DMA Frame Count reg-

ister (PacketPage base + 0028h).

2. New frames have been transferred via DMA,

and the host reads the BufEvent register

(either directly or from the ISQ) and sees that

the RxDMAFrame bit is set (this condition is

termed an "implied Skip").

3. The host issues a Reset-DMA command by

setting the ResetRxDMA bit (Register 17,

BusCTL, Bit 6).

5.4.6 DMA Buffer Organization

When DMA is used to transfer receive frames,

the DMA Start-of-Frame register (PacketPage

Base + 0026h) defines the offset from the DMA

base to the start of the most recently transferred

received frame. Frames stored in the DMA buff-

er are transferred as words and maintain

double-word (32-bit) alignment. Unfilled mem-

ory space between successive frames stored in

the DMA buffer may result from double-word

alignment. These "holes" may be 1, 2, or 3 bytes,

depending on the length of the frame preceding

the hole.

5.4.7 RxDMAFrame Bit

The RxDMAFrame bit (Register C, BufEvent,

bit 7) is controlled by the CS8900 and is set

whenever the value in the DMA Frame Count

register is non-zero. The host cannot clear

RxDMAFrame by reading the BufEvent register

(Register C). Table 5.9 summarizes the criteria

used to set and clear RxDMAFrame.

5.4.8 Receive DMA Example Without

Wrap-Around

Figure 5.6 shows three frames stored in host

memory by DMA without wrap-around.

5.4.9 Receive DMA Operation for

RxDMA-Only Mode

In an RxDMAOnly mode, a system DMA moves

all the received frames from the on-chip memory

to an external 16- or 64-Kbyte buffer memory.

The received frame must have passed the desti-

nation address filter, and must be completely

received. Usually, the DMA receive frame inter-

rupt (RxDMAiE, bit 7, Register B, BufCFG) is

set so that the CS8900 generates an interrupt

when a frame is transferred by DMA. Figure 5.7

shows how a DMA Receive Frame interrupt is

processed.

To Set RxDMAFrame

To Clear RxDMAFrame

Non-StreamTransfer Mode

StreamTransfer Mode (see Section 5.6)

The RxDMAFrame bit is set whenever the DMA The RxDMAFrame bit is set at the end of a

Frame Count register (PacketPage base + Stream Transfer cycle.

0028h) transitions to non-zero.

The DMA Frame Count is zero.

The DMA Frame Count is zero.

Table 5.9. RxDMAFrame Hit

DS150PP2

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