CS7654 查看數據表（PDF） - Cirrus Logic
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CS7654 Datasheet PDF : 62 Pages
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CS7654
Operational Control Register (06h at SA 0x34h)
7
res
Reserved
6
res
Reserved
5
res
Reserved
4
INREF
R/W
3
2
1
0
OE
POSPIX
EBLU
OBLU
R/W
R/W
R/W
R/W
OBLU
Logic high causes the first line after VREF of the odd field to be processed as a BLUE line. Logic
low causes the first line of the odd field to be processed as a RED line.
EBLU
Logic high causes the first line after VREF of the even field to be processed as a BLUE line.
Logic low causes the first line of the even field to be processed as a RED line.
POSPIX
Logic “1” causes the first pixel of the first line to be treated as a positive pixel in the color sep-
aration block. Logic “0” causes the first pixel to be treated as a negative pixel. Try toggling this
bit if the colors appear “reversed.”
OE
The Output Enable Bit operates in conjunction with the external HIZEN Pin, as illustrated in Ta-
ble 15.
INREF
OE Bit
0
0
1
1
HIZEN Pin
0
1
0
1
Digital Outputs
High-Z
High-Z
High-Z
Enabled
Table 15. OE Pin and Bit Operation
Logic “1” causes CS7654 to accept HREF input and VREF input pins as the reference inputs
signals. EAV and SAV codes in the CCD data stream are ignored. Logic “0” causes the internal
de-formatter to decode and follow the embedded EAV and SAV codes sent from the CCD dig-
itizer (as with the CS7615).
Operational Control Register II (07h at SA 0x34h)
7
TEST_AA
R/W
CLIP_OFF
6
CLIP_OFF
R/W
5
res
Reserved
4
res
Reserved
3
res
Reserved
2
res
Reserved
1
res
Reserved
0
res
Reserved
When set, excludes only 00 and FF from output data. Otherwise ITU BT 601 definition
TEST_AA
This bit is reserved for test purposes and may be set as a 1 or a 0.
Red Balance Register (08h at SA 0x34h)
7
6
5
4
3
2
1
0
RB7
RB6
RB5
RB4
RB3
RB2
RB1
RB0
R/W
RB[7:0]
The Red Balance register controls the red contribution to the R-Y chrominance signal. When
the register value is 00h, the red contribution is minimized; when the register value is FFh, the
red contribution is maximized. When the AWB correction is in progress, this register value is
adjusted such that the absolute magnitude of the R-Y signal is minimized.
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