CS7615 查看數據表（PDF） - Cirrus Logic
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CS7615 Datasheet PDF : 36 Pages
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CS7615
Timing Control - Charge Read Out in Even Field V3X Registers (59h-5Bh)
59h:
7
V3EF9
r/w
6
V3EF8
r/w
5
V3EF7
r/w
4
V3EF6
r/w
3
V3EF5
r/w
2
V3EF4
r/w
5Ah:
7
V3ER7
r/w
6
V3ER6
r/w
5
V3ER5
r/w
4
V3ER4
r/w
3
V3ER3
r/w
2
V3ER2
r/w
5Bh:
7
6
5
4
3
2
res
res
res
res
res
res
r
r
r
r
r
r
Charge readout timing for V3X in an even field in number of pixels.
V3EF
From HREF to leading edge of V3X. Default is 188h.
V3ER
From HREF to trailing edge of V3X. Default is 3Bh.
Timing Control - Charge Read Out in Even Field V4X Registers (5Ch-5Eh)
5Ch:
7
V4EF9
r/w
6
V4EF8
r/w
5
V4EF7
r/w
4
V4EF6
r/w
3
V4EF5
r/w
2
V4EF4
r/w
5Dh:
7
V4ER7
r/w
6
V4ER6
r/w
5
V4ER5
r/w
4
V4ER4
r/w
3
V4ER3
r/w
2
V4ER2
r/w
5Eh:
7
6
5
4
3
2
res
res
res
res
res
res
r
r
r
r
r
r
Charge readout timing for V4X in an even field in number of pixels.
V4EF
From HREF to leading edge of V4X. Default is 1E9h.
V4ER
From HREF to trailing edge of V4X. Default is 45h.
1
V3EF3
r/w
1
V3ER1
r/w
1
V3EF1
r/w
1
V4EF3
r/w
1
V4ER1
r/w
1
V4EF1
r/w
0
V3EF2
r/w
0
V3ER0
r/w
0
V3EF0
r/w
0
V4EF2
r/w
0
V4ER0
r/w
0
V4EF0
r/w
DS231PP6
27
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