CS7615 查看數據表（PDF） - Cirrus Logic
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CS7615 Datasheet PDF : 36 Pages
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CS7615
Timing Control - HENB Registers (46h-47h)
46h:
7
HEND7
r/w
6
HEND6
r/w
5
HEND5
r/w
4
HEND4
r/w
3
HEND3
r/w
2
HEND2
r/w
1
HEND1
r/w
47h:
7
HSTART7
r/w
6
HSTART6
r/w
5
HSTART5
r/w
4
HSTART4
r/w
3
HSTART3
r/w
2
HSTART2
r/w
1
HSTART1
r/w
HEND
Number of pixels from HREF to leading edge of HENB. Default is 1Ch.
HSTART
Number of pixels from HREF to trailing edge of HENB. Default is 68h.
Timing Control - V1X Registers (48h-49h)
48h:
7
V1R7
r/w
6
V1R6
r/w
5
V1R5
r/w
4
V1R4
r/w
3
V1R3
r/w
2
V1R2
r/w
1
V1R1
r/w
49h:
7
V1F7
r/w
6
V1F6
r/w
5
V1F5
r/w
4
V1F4
r/w
3
V1F3
r/w
2
V1F2
r/w
1
V1F1
r/w
V1X is a vertical register shift clock.
V1R
Number of pixels from HREF to leading edge of V1X. Default is 22h.
V1F
Number of pixels from HREF to trailing edge of V1X. Default is 36h.
0
HEND0
r/w
0
HSTART0
r/w
0
V1R0
r/w
0
V1F0
r/w
DS231PP6
23
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