CS7615 查看數據表（PDF） - Cirrus Logic
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CS7615 Datasheet PDF : 36 Pages
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CS7615
Timing Control - V4X Registers (4Eh-4Fh):
4Eh:
7
V4F7
r/w
6
V4F6
r/w
5
V4F5
r/w
4
V4F4
r/w
3
V4F3
r/w
2
V4F2
r/w
1
V4F1
r/w
4Fh:
7
V4R7
r/w
6
V4R6
r/w
5
V4R5
r/w
4
V4R4
r/w
3
V4R3
r/w
2
V4R2
r/w
1
V4R1
r/w
V4X is a vertical register shift clock.
V4F
Number of pixels from HREF to leading edge of V4X. Default is 29h.
V4R
Number of pixels from HREF to trailing edge of V4X. Default is 45h.
Timing Control - Charge Read Out in Odd Field V2X Registers (50h-52h)
50h:
7
V2OR9
r/w
6
V2OR8
r/w
5
V2OR7
r/w
4
V2OR6
r/w
3
V2OR5
r/w
2
V2OR4
r/w
1
V2OR3
r/w
51h:
7
V2OF9
r/w
6
V2OF8
r/w
5
V2OF7
r/w
4
V2OF6
r/w
3
V2OF5
r/w
2
V2OF4
r/w
1
V2OF3
r/w
52h:
7
6
5
4
3
2
1
res
res
res
res
V2OF1
V2OF0
V2OR1
r
r
r
r
r/w
r/w
r/w
Charge readout timing for V2X in an odd field in number of pixels.
V2OR
From HREF to leading edge of V2X. Default is 185h.
V2OF
From HREF to trailing edge of V2X. Default is 1E9h.
0
V4F0
r/w
0
V4R0
r/w
0
V2OR2
r/w
0
V2OF2
r/w
0
V2OR0
r/w
DS231PP6
25
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