AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
AT89C51CC03C-RLTIM Datasheet PDF : 197 Pages
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Bit
Bit
Number Mnemonic Description
Mode Fault
- Set by hardware to indicate that the SS pin is in inappropriate logic level (in both
master and slave modes).
- Cleared by hardware when reading SPSCR
4
MODF When MODF error occurred:
- In slave mode: SPI interface ignores all transmitted data while SS remains high.
A new transmission is perform as soon as SS returns low.
- In master mode: SPI interface is disabled (SPEN=0, see description for SPEN
bit in SPCON register).
Serial Peripheral Transmit register Empty
- Set by hardware when transmit register is empty (if needed, SPDAT can be
3
SPTE loaded with another data).
- Cleared by hardware when transmit register is full (no more data should be
loaded in SPDAT).
Serial Peripheral UART mode
Set and cleared by software:
2
UARTM
- Clear: Normal mode, data are transmitted MSB first (default)
- Set: UART mode, data are transmitted LSB first.
Interrupt Enable for SPTE
Set and cleared by software:
- Set to enable SPTE interrupt generation (when SPTE goes high, an interrupt is
1
SPTEIE generated).
- Clear to disable SPTE interrupt generation
Caution: When SPTEIE is set no interrupt generation occurred when SPIF flag
goes high. To enable SPIF interrupt again, SPTEIE should be cleared.
Interrupt Enable for MODF
Set and cleared by software:
0
MODFIE
- Set to enable MODF interrupt generation
- Clear to disable MODF interrupt generation
Reset Value = 00X0 XXXXb
Not Bit addressable
Serial Peripheral DATa Register
(SPDAT)
The Serial Peripheral Data Register (Table 94) is a read/write buffer for the receive data
register. A write to SPDAT places data directly into the shift register. No transmit buffer is
available in this model.
A Read of the SPDAT returns the value located in the receive buffer and not the content
of the shift register.
Table 94. SPDAT Register
SPDAT - Serial Peripheral Data Register (0C5H)
7
6
5
4
3
2
1
0
R7
R6
R5
R4
R3
R2
R1
R0
Reset Value = Indeterminate
R7:R0: Receive data bits
140 AT89C51CC03
4182K–CAN–05/06
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