AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
AT89C51CC03C-RLTIM Datasheet PDF : 197 Pages
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Figure 66. SPI Interrupt Requests Generation
SPIF
SPTEIE
SPTE
MODFIE
MODF
SPI
CPU Interrupt Request
Registers
Serial Peripheral Control
Register (SPCON)
Three registers in the SPI module provide control, status and data storage functions.
These registers are describe in the following paragraphs.
• The Serial Peripheral Control Register does the following:
• Selects one of the Master clock rates
• Configure the SPI Module as Master or Slave
• Selects serial clock polarity and phase
• Enables the SPI Module
• Frees the SS pin for a general-purpose
Table 92 describes this register and explains the use of each bit
Table 92. SPCON Register
SPCON - Serial Peripheral Control Register (0D4H)
7
6
5
4
3
SPR2
SPEN
SSDIS
MSTR
CPOL
2
CPHA
1
SPR1
0
SPR0
Bit Number
7
6
5
4
Bit Mnemonic
SPR2
SPEN
SSDIS
MSTR
Description
Serial Peripheral Rate 2
Bit with SPR1 and SPR0 define the clock rate (See bits SPR1 and
SPR0 for detail).
Serial Peripheral Enable
Cleared to disable the SPI interface (internal reset of the SPI).
Set to enable the SPI interface.
SS Disable
Cleared to enable SS in both Master and Slave modes.
Set to disable SS in both Master and Slave modes. In Slave mode,
this bit has no effect if CPHA =’0’. When SSDIS is set, no MODF
interrupt request is generated.
Serial Peripheral Master
Cleared to configure the SPI as a Slave.
Set to configure the SPI as a Master.
138 AT89C51CC03
4182K–CAN–05/06
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