AT89C51CC03C-RLTIM View Datasheet(PDF) - Atmel Corporation
Part Name
Description
MFG CO.
AT89C51CC03C-RLTIM Datasheet PDF : 197 Pages
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Figure 60. Data Transmission Format (CPHA = 0)
SCK Cycle Number
1
2
3
4
5
6
7
8
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MISO (from Slave)
SS (to Slave)
Capture Point
MSB
MSB
bit6
bit5
bit4
bit3
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit2
bit1
LSB
Figure 61. Data Transmission Format (CPHA = 1)
SCK Cycle Number
1
2
3
4
5
6
7
8
SPEN (Internal)
SCK (CPOL = 0)
SCK (CPOL = 1)
MOSI (from Master)
MISO (from Slave)
SS (to Slave)
Capture Point
MSB
bit6
bit5
bit4
bit3
MSB
bit6
bit5
bit4
bit3
bit2
bit1
LSB
bit2
bit1
LSB
Figure 62. CPHA/SS Timing
MISO/MOSI
Byte 1
Byte 2
Byte 3
Master SS
Slave SS
(CPHA = 0)
Slave SS
(CPHA = 1)
As shown in Figure 60, the first SCK edge is the MSB capture strobe. Therefore, the
Slave must begin driving its data before the first SCK edge, and a falling edge on the SS
pin is used to start the transmission. The SS pin must be toggled high and then low
between each Byte transmitted (Figure 62).
Figure 61 shows an SPI transmission in which CPHA is ’1’. In this case, the Master
begins driving its MOSI pin on the first SCK edge. Therefore, the Slave uses the first
SCK edge as a start transmission signal. The SS pin can remain low between transmis-
sions (Figure 62). This format may be preferred in systems having only one Master and
only one Slave driving the MISO data line.
Queuing transmission
For an SPI configured in master or slave mode, a queued data byte must be transmit-
ted/received immediately after the previous transmission has completed.
134 AT89C51CC03
4182K–CAN–05/06
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