CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

15. JTAG TEST PORT (IEEE 1149.1)

The CS5376 includes a JTAG test port for bound-

ary scan testing. Boundary scan testing checks the

interconnections of a design by writing and reading

data directly from the pins using an on-chip JTAG

controller. For a detailed description of the oper-

ation of the JTAG port, refer to the IEEE 1149.1

specification.

15.1 JTAG Pin Definitions

TRST - Pin 1

Resets the test access port controller and all bound-

ary scan cells in the scan chain. This pin includes a

weak pullup resistor to provide a power on reset if

not driven by a signal source.

TMS - Pin 2

The test mode of the JTAG controller is selected by

a serial write to this pin using TCK.

TCK - Pin 3

Clock input for the test access port controller.

TDI - Pin 4

Serial data input to the boundary scan chain or test

access port controller.

TDO - Pin 5

Serial data output from the boundary scan chain or

test access port controller.

15.2 JTAG Architecture

The JTAG test circuitry consists of a test access

port (TAP) controller and boundary scan cells

within each pin. The boundary scan cells are linked

together to create a scan chain around the CS5376.

15.2.1 TAP Controller

The test access port (TAP) controller manages seri-

al scanning of instruction and data information

through the CS5376. The TAP controller uses the

16 JTAG state assignments from the IEEE 1149.1

specification which are sequenced based on the

state of the TMS pin on the rising edge of TCK.

The TAP controller generates signals for capture,

shift, and update operations on the internal instruc-

TRST - Test Reset, pin 1

JTAG reset input pin, resets the test access port controller (TAP).

TMS - Test Mode Select, pin 2

JTAG mode select input pin, control signal to the test access port controller (TAP).

TCK - Test Clock, pin 3

JTAG clock input pin, clocks the test access port controller (TAP).

TDI - Test Data Input, pin 4

JTAG data input pin, the path by which serial data enters the device.

TDO - Test Data Output, pin 5

JTAG data output pin, the path by which serial data exits the device.

Figure 62. JTAG Pins

DS256PP1

89

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