CS5376-BS View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS5376-BS Datasheet PDF : 122 Pages
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CS5376
13.3 TBS Data Source
When enabled, the TBS generator has input data
periodically written by the decimation engine. The
source of the data can either be an internal 1024
point sine-wave or a user programmed data set of
up to 1024 points.
13.3.1 TBS ROM Data
The CS5376 has a 24-bit 1024 point digital sine-
wave stored internally. This data can be specified
to be used by the test bit stream generator during
the initial boot configuration of the CS5376. Both
the coprocessor and stand-alone boot modes in-
clude a command, ‘Write TBS ROM Data’, to ini-
tialize the internal data set for use by the test bit
stream generator. See “Serial Peripheral Interface
1” on page 21 for information about boot modes
and configuration commands.
Using the internal data set, the TBS generator can
produce many test signal frequencies between 2 Hz
and 125 Hz. When used in digital loopback mode,
the TBS generator produces a 1-bit 512 kHz output
bit stream suitable for the digital filter input. Figure
56 lists selected test signal frequencies that can be
generated for digital filter loopback using the in-
cluded TBS data set. Other test frequencies and
output rates can be programmed using the internal
data set by varying the internal clock rate and inter-
polation factor.
13.3.2 TBS Uploaded Data
If a specific test frequency is required that cannot
be generated using the internal test bit stream data
set, a custom data set can be written into the
CS5376. Both the coprocessor and stand-alone
boot modes include a command, ‘Write TBS Data’,
to write a custom TBS data set up to 1024 points.
The number of data points written will depend on
the test signal frequency to be generated, the re-
quired output clock frequency, and the available in-
terpolation factors. Note that any custom data set
must be continuous on the ends; i.e. when copied
end-to-end the data set must produce a smooth
curve.
13.4 TBS Configuration
After a TBS data source has been specified, the test
bit stream generator is configured by writing the
TBS_CFG register (0x2A).
Test Signal
Frequency
(TBSDATA)
2.00 Hz
5.00 Hz
10.00 Hz
25.00 Hz
31.25 Hz
33.33 Hz
50.00 Hz
62.50 Hz
100.00 Hz
125.00 Hz
Output Clock
Rate
(TBSCLK)
512 kHz
512 kHz
512 kHz
512 kHz
512 kHz
512 kHz
512 kHz
512 kHz
512 kHz
512 kHz
Internal Clock
Rate
(RATE)
4.096 MHz
4.096 MHz
4.096 MHz
4.096 MHz
4.096 MHz
4.096 MHz
4.096 MHz
4.096 MHz
4.096 MHz
4.096 MHz
Interpolation
Factor
(INTP)
0xF9
0x63
0x31
0x13
0x0F
0x0E
0x09
0x07
0x04
0x03
Figure 56. Selected TBS Settings for 512 kHz Output
DS256PP1
82
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