CS5376-BS View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS5376-BS

Low Power Multi-Channel Decimation Filter

Cirrus Logic 

CS5376

13. TEST BIT STREAM GENERATOR

The CS5376 includes a test bit stream (TBS) gen-

erator designed to drive an off-chip test DAC. The

TBS output can also be internally connected to the

digital filter input for loopback testing.

The test bit stream generator output is programma-

ble and the exact configuration depends on the type

of test DAC used. When used in digital loopback

mode the output will be 1-bit at 512 kHz. Many test

signal frequencies between 2 Hz and 125 Hz (in-

cluding 31.25 Hz) can be generated using the inter-

nal data set. Test frequencies between 2 Hz and 125

Hz that cannot be generated using the internal data

set can be generated by writing a custom data set.

which receives periodic 24-bit input data from the

decimation engine. The test bit stream generator

outputs a data clock to the TBSCLK pin and a 1-bit

∆-Σ modulated bit stream to the TBSDATA pin.

The test bit stream generator runs from an internal

clock set in the TBS_CFG register (0x2A). The

output clock rate on the TBSCLK pin is 1/8 the se-

lected internal clock rate. A delay can be intro-

duced to the output clock to align it with any rising

edge of the internal clock, a resolution of 1/8 the

output clock period. Data output from the TBSDA-

TA pin also has a programmable delay, up to 64 in-

ternal clock periods.

13.1 TBS Generator Architecture

The test bit stream generator incorporates a data in-

terpolation module and a digital ∆-Σ modulator

Decimation Engine

Data Bus

24b @ 1 Fs

Interpolator

24b @ 64 Fs

Digital ∆Σ Modulator

1b @ 512 Fs

TBSDATA

Figure 54. Digital TBS Data Path

13.2 TBS Pin Descriptions

TBSCLK - Pin 8

Test bit stream output clock. Output rate is 1/8 the

programmed internal test bit stream generator

clock rate. Can be delayed up to 8 internal clock pe-

riods.

TBSDATA - Pin 9

Test bit stream output data. Can be delayed up to 64

internal clock periods.

Loopback - Internal

Internal connection providing a data path from the

test bit stream generator output to the digital filter

input.

TBSCLK - Test Signal Modulator Clock Output, pin 8

A dedicated clock output pin to interface with an external ∆−Σ test DAC.

TBSDATA - Test Signal Modulator Data Output, pin 9

A dedicated data output pin to interface with an external ∆−Σ test DAC.

Figure 55. Test Bit Stream Pins

DS256PP1

81

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