
PIC16F913/914/916/917/946
FIGURE 3-26:
Data Bus
WR PORTE
WR TRISE
BLOCK DIAGRAM OF RE<2:0> (PIC16F914/917 AND PIC16F946 ONLY)
VDD
DQ
CK Q
Data Latch
DQ
CK Q
TRIS Latch
RD TRISE
Analog Mode or
SEG<23:21> and LCDEN
and LCDEN
Schmitt
Trigger
I/O Pin
VSS
RD PORTE
SEG<23:21>
AN<7:5>
SEG<23:21> and LCDEN
FIGURE 3-27:
BLOCK DIAGRAM OF RE3
MCLR circuit
Programming mode
MCLR Filter
HV Detect
Data Bus
RD TRISE
VSS
HV
Schmitt Trigger
Buffer
MCLRE
Input Pin
VSS
HV
Schmitt Trigger
Buffer
RD PORTE
DS41250F-page 78
© 2007 Microchip Technology Inc.