
PIC16F913/914/916/917/946
FIGURE 3-22:
BLOCK DIAGRAM OF RD0
Data Bus
WR PORTD
WR TRISD
DQ
CK Q
Data Latch
DQ
CK Q
TRIS Latch
VDD
I/O Pin
VSS
RD TRISD LCDEN and LMUX<1:0> = 11
RD PORTD
COM3
LCDEN and
LMUX<1:0> = 11
Schmitt
Trigger
FIGURE 3-23:
BLOCK DIAGRAM OF RD1
Data Bus
WR PORTD
WR TRISD
DQ
CK Q
Data Latch
DQ
CK Q
TRIS Latch
RD TRISD
VDD
RD1 Pin
VSS
Schmitt
Trigger
RD PORTD
© 2007 Microchip Technology Inc.
DS41250F-page 73