
PIC16F913/914/916/917/946
FIGURE 3-24:
BLOCK DIAGRAM OF RD2
(PORT/CCP2 Select) and CCPMX
CCP2 Data Out
0
Data Bus
DQ
1
WR PORTD
CK Q
Data Latch
WR TRISD
DQ
CK Q
TRIS Latch
RD TRISD
Schmitt
Trigger
RD PORTD
CCP2 Input
VDD
I/O Pin
VSS
FIGURE 3-25:
BLOCK DIAGRAM OF RD<7:3>
Data Bus
WR PORTD
WR TRISD
D
Q
CK Q
Data Latch
DQ
CK Q
TRIS Latch
RD TRISD
SE<20:16> and LCDEN
Schmitt
Trigger
VDD
I/O Pin
VSS
RD PORTD
SEG<20:16>
SE<20:16> and LCDEN
DS41250F-page 74
© 2007 Microchip Technology Inc.