QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

AC Characteristics

The AC characteristics are calculated at 2.5 V, TA = 25°C (K = 0.74). To calculate delays, multiply

the appropriate K factor in Table 17 by the numbers presented in Table 20 through Table 27.

Table 20: Logic Cells

Symbol

Logic Cells

Parameter

tPD

Combinatorial Delay of the Longest Path: time taken by the combinatorial

circuit to output

tSU

Setup Time: time the synchronous input of the flip flop must be stable before the

active clock edge

tHL

Hold Time: time the synchronous input of the flip flop must be stable after the

active clock edge

tCO

Clock to Out Delay: the amount of time taken by the flip flop to output after the

active clock edge.

tCWHI

tCWLO

tSET

Clock High Time: required minimum time the clock stays high

Clock Low Time: required minimum time that the clock stays low

Set Delay: time between when the flip flop is ”set” (high) and when the output is

consequently “set” (high)

tRESET

Reset Delay: time between when the flip flop is ”reset” (low) and when the output

is consequently “reset” (low)

tSW

Set Width: time that the SET signal remains high/low

tRW

Reset Width: time that the RESET signal remains high/low

Value (ns)

Min Max

- 0.257

0.22

-

0

-

- 0.255

0.46

-

0.46

-

-

0.18

-

0.09

0.3

-

0.3

-

SET

D

Q

CLK

RESET

Figure 9: Logic Cell

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20

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© 2003 QuickLogic Corporation

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