QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

PLL Modes of Operation

QuickLogic PLLs have eight modes of operation, based on the input frequency and desired output

frequency—Table 14 indicates the features of each mode.

NOTE: "HF" stands for "high frequency" and "LF" stands for "low frequency."

PLL Model

PLL_HF

PLL_LF

PLL_MULT2HF

PLL_MULT2LF

PLL_DIV2HF

PLL_DIV2LF

PLL_MULT4

PLL_DIV4

Table 14: PLL Mode Frequencies

Output

Frequency

Input Frequency Range

Same as input

66 MHz–150 MHz

Same as input

25 MHz–133 MHz

2x

50 MHz–125 MHz

2x

16 MHz–50 MHz

1/2x

100 MHz–250 MHz

1/2x

50 MHz–100 MHz

4x

16 MHz–40 MHz

1/4x

100 MHz–300 MHz

Output Frequency Range

66 MHz–150 MHz

25 MHz–133 MHz

100 MHz–250 MHz

32 MHz–100 MHz

50 MHz–125 MHz

25 MHz–50 MHz

64 MHz–160 MHz

25 MHz–75 MHz

NOTE: The input frequency can range from 16 MHz to 300 MHz, while output frequency

ranges from 25 MHz to 250 MHz. When you add PLLs to your top-level design, be sure

that the PLL mode matches your desired input and output frequencies.

PLL Signals

Table 15 summarizes the key signals in QuickLogic's PLLs.

Table 15: PLL Signals

Signal Name

Description

PLLCLK_IN Input clock signal

PLL_RESET

Active High Reset If PLL_RESET is asserted, then CLKNET_OUT and

PLLPAD_OUT are reset to 0. This signal must be asserted and then released

in order for the LOCK_DETECT to work.

ONn_OFFCHIP

PLL output This signal selects whether the PLL will drive the internal clock

network or be used off-chip. This is a static signal, not a dynamic signal.

Tied to GND = outgoing signal drives internal gates.

Tied to VCC = outgoing signal used off-chip.

Out to internal gates This signal bypasses the PLL logic before driving the

CLKNET_OUT internal gates. Note that this signal cannot be used in the same quadrant where

the PLL signal is used (PLLCLK_OUT).

© 2003 QuickLogic Corporation

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