QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

Table 15: PLL Signals (Continued)

Signal Name

Description

PLLCLK_OUT

Out from PLL to internal gates This signal can drive the internal gates after

going through the PLL. For this to work, ONn_OFFCHIP must be tied to GND.

PLLPAD_OUT

Out to off-chip This outgoing signal is used off-chip. For this to work,

ONn_OFFCHIP signal must be tied to VCC.

Active High Lock detection signal NOTE: For simulation purposes, this

LOCK_DETECT signal gets asserted after 10 clock cycles. However, it can take a maximum of

200 clock cycles to sync with the input clock upon release of the RESET signal.

NOTE: Because PLLCLK_IN and PLL_RESET signals have INPAD, and PLLPAD_OUT has

OUTPAD, you do not have to add additional pads to your design.

JTAG Support

TCK

TMS

TRSTB

TAp Controller

State Machine

(16 States)

Instruction Decode

&

Control Logic

RDI

Mux

Instruction Register

Boundary-Scan Register

(Data Register)

Mux

TDO

Bypass

Register

Internal

Register

I/O Registers

User Defined Data Register

Figure 7: JTAG Block Diagram

The Joint Test Access Group (JTAG) pins support the IEEE Standard 1149.1a to provide

boundary scan capability for the QL6432 device. Six pins are dedicated to JTAG and

programming functions on each QL6432 device; these pins are unavailable for general design

input and output signals. TDI, TDO, TCK, TMS, and TRSTB are JTAG pins. The sixth pin, STM,

is used only for programming.

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© 2003 QuickLogic Corporation

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