QL5632(2003) View Datasheet(PDF) - QuickLogic Corporation

Part Name

Description

MFG CO.

QL5632
(Rev.:2003)

33 MHz/32-bit PCI Master/Target with Embedded Programmable Logic and Dual Port SRAM

QuickLogic Corporation 

QL5632 Enhanced QuickPCI Device Data Sheet Rev. C

Microprocessors and Application Specific Integrated Circuits (ASICs) pose many design

challenges. One of these challenges concerns the accessibility of test points. JTAG was formed in

response to this challenge, resulting in IEEE standard 1149.1, the Standard Test Access Port and

Boundary Scan Architecture.

The JTAG boundary scan test methodology allows complete observation and control of the

boundary pins of a JTAG-compatible device through JTAG software. A Test Access Port (TAP)

controller works in concert with the Instruction Register (IR); these allow users to run three

required tests, along with several user-defined tests.

JTAG tests allow users to reduce system debug time, reuse test platforms and tools, and reuse

subsystem tests for fuller verification of higher level system elements.

The JTAG 1149.1 standard requires the following three tests:

• Extest Instruction. The Extest instruction performs a PCB interconnect test. This test

places a device into an external boundary test mode, selecting the boundary scan register to

be connected between the TAP's Test Data In (TDI) and Test Data Out (TDO) pins. Boundary

scan cells are preloaded with test patterns (via the Sample/Preload Instruction), and input

boundary cells capture the input data for analysis.

• Sample/Preload Instruction. This instruction allows a device to remain in its functional

mode, while selecting the boundary scan register to be connected between the TDI and TDO

pins. For this test, the boundary scan register can be accessed via a data scan operation,

allowing users to sample the functional data entering and leaving the device.

• Bypass Instruction. The Bypass instruction allows data to skip a device's boundary scan

entirely, so the data passes through the bypass register. The Bypass instruction allows users

to test a device without passing through other devices. The bypass register connects the TDI

and TDO pins, allowing serial data to be transferred through a device without affecting the

operation of the device.

Development Tool Support

Software support for the QL6432 device is available through the QuickWorks development

package. This turnkey PC-based QuickWorks package, shown in Figure 8, provides a complete

ESP software solution with design entry, logic synthesis, place and route, and simulation.

QuickWorks includes VHDL, Verilog, schematic, and mixed-mode entry with fast and efficient

logic synthesis provided by the integrated Synplicity Synplify Lite tool which is specially tuned

to take advantage of the QL6432 architecture. QuickWorks also provides functional and timing

simulation for guaranteed timing and source-level debugging.

The UNIX-based QuickTools package is a subset of QuickWorks and provides a solution for

designers who use schematic-only design flow third-party tools for design entry, synthesis, or

simulation. QuickTools Reads EDIF netlists and provides support for all QuickLogic devices.

QuickTools also supports a wide range of third-party modeling and simulation tools.

© 2003 QuickLogic Corporation

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