ISPXPLD5256MX View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

MFG CO.

ISPXPLD5256MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

Boundary Scan Timing Specifications

Over Recommended Operating Conditions

Parameter

tBTCP

tBTCPH

tBTCPL

tBTS

tBTH

tBTRF

tBTCO

tBTCODIS

tBTCOEN

tBTCRS

tBTCRH

tBUTCO

tBTUODIS

tBTUPOEN

Description

TCK [BSCAN] clock pulse width

TCK [BSCAN] clock pulse width high

TCK [BSCAN] clock pulse width low

TCK [BSCAN] setup time

TCK [BSCAN] hold time

TCK [BSCAN] rise/fall time

TAP controller falling edge of clock to valid output

TAP controller falling edge of clock to valid disable

TAP controller falling edge of clock to valid enable

BSCAN test capture register setup time

BSCAN test capture register hold time

BSCAN test update register, falling edge of clock to valid output

BSCAN test update register, falling edge of clock to valid disable

BSCAN test update register, falling edge of clock to valid enable

Min

Max Units

40

—

ns

20

—

ns

20

—

ns

8

—

ns

10

—

ns

50

—

mV/ns

—

10

ns

—

10

ns

—

10

ns

8

—

ns

10

—

ns

—

25

ns

—

25

ns

—

25

ns

45

Share Link: