ISPXPLD5256MX View Datasheet(PDF) - Lattice Semiconductor

Part Name

Description

MFG CO.

ISPXPLD5256MX

3.3V, 2.5V and 1.8V In-System Programmable eXpanded Programmable Logic Device XPLD™ Family

Lattice Semiconductor 

Lattice Semiconductor

ispXPLD 5000MX Family Data Sheet

Switching Test Conditions

Figure 21 shows the output test load that is used for AC testing. The specific values for resistance, capacitance,

voltage, and other test conditions are shown in Table 14.

Figure 21. Output Test Load, LVTTL and LVCMOS Standards

VCCO

R1

Device

Output

Test

Point

R2

CL*

*CL includes test fixture and probe capacitance.

Table 14. Test Fixture Required Components

Test Condition

R1

Default LVCMOS 1.8 I/O (L -> H, H -> L) 106

R2

CL

106 35pF

Timing Ref.

VCCO/2

LVCMOS3.3 = 1.5V

LVCMOS I/O (L -> H, H -> L)

—

—

35pF LVCMOS2.5 = VCCO/2

LVCMOS1.8 = VCCO/2

Default LVCMOS 1.8 I/O (Z -> H)

—

106 35pF

VCCO/2

Default LVCMOS 1.8 I/O (Z -> L)

106

— 35pF

VCCO/2

Default LVCMOS 1.8 I/O (H -> Z)

—

106 5pF

VOH - 0.15

Default LVCMOS 1.8 I/O (L -> Z)

106

—

5pF

VOL + 0.15

Note: Output test conditions for all other interfaces are determined by the respective standards.

VCCO

1.8V

LVCMOS3.3 = 3.0V

LVCMOS2.5 = 2.3V

LVCMOS1.8 = 1.65V

1.65V

1.65V

1.65V

1.65V

48

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