PC48F2000P0VB00 View Datasheet(PDF) - Intel

Part Name

Description

MFG CO.

PC48F2000P0VB00

Intel StrataFlash® Embedded Memory

Intel 

1-Gbit P30 Family

10.3.9

boundary, the worst case output delay is one clock cycle less than the first access Latency Count.

This delay can take place only once, and doesn’t occur if the burst sequence does not cross a

device-row boundary. WAIT informs the system of this delay when it occurs.

Burst Length

The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst reads of the

flash memory array. The burst lengths are 4-word, 8-word, 16-word, and continuous word.

Continuous-burst accesses are linear only, and do not wrap within any word length boundaries (see

Table 25, “Burst Sequence Word Ordering” on page 59). When a burst cycle begins, the device

outputs synchronous burst data until it reaches the end of the “burstable” address space.

April 2005

60

Intel StrataFlash® Embedded Memory (P30)

Order Number: 306666, Revision: 001

Datasheet

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