PC48F2000P0VB00 View Datasheet(PDF) - Intel
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MFG CO.
PC48F2000P0VB00 Datasheet PDF : 102 Pages
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1-Gbit P30 Family
Table 24. WAIT Functionality Table
Condition
WAIT
CE# = ‘1’, OE# = ‘X’ or CE# = ‘0’, OE# = ‘1’
High-Z
CE# =’0’, OE# = ‘0’
Active
Synchronous Array Reads
Active
Synchronous Non-Array Reads
Active
All Asynchronous Reads
Deasserted
All Writes
High-Z
Notes:
1.
Active: WAIT is asserted until data becomes valid, then deasserts
2.
When OE# = VIH during writes, WAIT = High-Z
Notes
1
1
1
1
1
1,2
10.3.4
Figure 30.
Data Hold
For burst read operations, the Data Hold (DH) bit determines whether the data output remains valid
on DQ[15:0] for one or two clock cycles. This period of time is called the “data cycle”. When DH
is set, output data is held for two clocks (default). When DH is cleared, output data is held for one
clock (see Figure 30). The processor’s data setup time and the flash memory’s clock-to-data output
delay should be considered when determining whether to hold output data for one or two clocks. A
method for determining the Data Hold configuration is shown below:
To set the device at one clock data hold for subsequent reads, the following condition must be
satisfied:
tCHQV (ns) + tDATA (ns) ≤ One CLK Period (ns)
tDATA = Data set up to Clock (defined by CPU)
For example, with a clock frequency of 40 MHz, the clock period is 25 ns. Assuming
tCHQV = 20 ns and tDATA = 4 ns. Applying these values to the formula above:
20 ns + 4 ns ≤ 25 ns
The equation is satisfied and data will be available at every clock period with data hold setting at
one clock. If tCHQV (ns) + tDATA (ns) > One CLK Period (ns), data hold setting of 2 clock periods
must be used.
Data Hold Timing
CLK [C]
1 CLK
Data Hold
2 CLK
Data Hold
D[15:0] [Q]
D[15:0] [Q]
Valid
Output
Valid
Output
Valid
Output
Valid
Output
Valid
Output
April 2005
58
Intel StrataFlash® Embedded Memory (P30)
Order Number: 306666, Revision: 001
Datasheet
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