CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.4.3 PDDR Port D Data Register (address 0x8000.0003)

Values written to this 8-bit read / write register will be output on Port D pins if the corresponding data direc-

tion bits are set low (port output). Values read from this register reflect the external state of Port D, not nec-

essarily the value written to it. All bits are cleared by a system reset.

3.4.4 PADDR Port A Data Direction Register (address 0x8000.0040)

Bits set in this 8-bit read / write register will select the corresponding pin in Port A to become an output, clear-

ing a bit sets the pin to input. All bits are cleared by a system reset.

3.4.5 PBDDR Port B Data Direction Register (address 0x8000.0041)

Bits set in this 8-bit read / write register will select the corresponding pin in Port B to become an output, clear-

ing a bit sets the pin to input. All bits are cleared by a system reset.

3.4.6 PDDDR Port D Data Direction Register (address 0x8000.0043)

Bits cleared in this 8-bit read / write register will select the corresponding pin in Port D to become an output,

setting a bit sets the pin to input. All bits are cleared by a system reset so that Port D is output by default.

3.4.7 PEDR Port E Data Register (address 0x8000.0080)

Values written to this 3-bit read / write register will be output on Port E pins if the corresponding data direc-

tion bits are set high (port output). Values read from this register reflect the external state of Port E, not nec-

essarily the value written to it. All bits are cleared by a system reset.

3.4.8 PEDDR Port E Data Direction Register (address 0x8000.00C0)

Bits set in this 3-bit read / write register will select the corresponding pin in Port E to become an output, while

the clearing bit sets the pin to input. All bits are cleared by a system reset so that Port E is input by default.

3.5 System Control Registers

3.5.1 SYSCON1 The System Control Register 1 (address 0x8000.0100)

23:21

Reserved

14

CDENRX

8

UART1EN

20

IRTXM

13

CDENTX

7

TC2S

19

WAKEDIS

12

LCDEN

6

TC2M

18

EXCKEN

11

DBGEN

5

TC1S

17:16

ADCKSEL

10

BZMOD

4

TC1M

15

SIREN

9

BZTOG

3:0

Keyboard scan

The system control register is a 21-bit read / write register which controls all the general configuration of the

CS89712, as well as modes etc. for peripheral devices. All bits in this register are cleared by a system reset. The

bits in the system control register SYSCON1 are defined in Table 37.

DS502PP2

79

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