CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.3 Ethernet Port 4 Kbyte Memory Register Map

The following Table shows the CS89712 Ethernet Port internal register map:

Internal

Offset

# of

Bytes

Bus Interface Registers

0000h

4

0004h

28

0022h

2

Type

Description

Reserved

-

Reserved

RW Master Interrupt Enable

0038h

0040h

8

-

Reserved

2

RW EEPROM Command

0042h

2

RW EEPROM Data

0044h

0050h

12

-

2

RD

0052h

174

-

Status and Control Registers

0102

2

RW

0104

0106

0108

010A

0112

0114

0116

0118

0120

0124

0124

0128

012C

0130

0132

0134

0136

2

RW

2

RW

2

RW

2

RW

2

RW

2

RW

2

RW

2

RW

2

RD

2

RD

2

RD

2

RD

2

RD

2

RD

2

RD

2

RD

2

RD

Reserved

Received Frame Byte

Counter

Reserved

Receive Configuration

Receive Control

Transmit Configuration

Transmit Command

Buffer Configuration

Line Control

Self Control

Bus Control

Test Control

Interrupt Status Queue

Receive Event

alternate Receive Event

Transmit Event

Buffer Event

Receive Miss

Transmit Collision

Line Status

Self Status

Cross Reference

Note 2

Section 3., “REGISTER SET”,

Section 3.17, “Ethernet Bus Interface Reg-

isters”

Note 2

Section 2.24, “Programming the EEPROM”,

Section 3.17, “Ethernet Bus Interface Reg-

isters”

Section 2.24, “Programming the EEPROM”,

Section 3.17, “Ethernet Bus Interface Reg-

isters”

Note 2

Section 3.17, “Ethernet Bus Interface Reg-

isters”,

Section 2.32, “Basic Receive Operation”

Note 2

Section 3.2.3, “Ethernet Status/Control

Registers”

see above

see above

see above

see above

see above

see above

see above

see above

Table 36. Ethernet Port 4 Kbyte Memory Register Address Map

DS502PP2

77

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