CS89712-CB View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS89712-CB Datasheet PDF : 170 Pages
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CS89712
3.2.5 Status and Event Registers
Status and Event registers report the status of trans-
mitted and received frames, as well as information
about the configuration of the CS89712. They are
read-only.
The Interrupt Status Queue (ISQ) is a special type
of Status/Event register. It is located at Ethernet
Port offset address 0120h and is the first register
the software reads when responding to an Interrupt.
A more detailed description of the ISQ can be
found in Section 2.31, “Managing Interrupts &
Status Queue”.
Three 10-bit counters are included with the Status
and Event registers. RxMISS counts missed re-
ceive frames, TxCOL counts transmit collisions.
Table 34 summarizes Ethernet Port Register types.
3.2.6 Status and Control Bit Definitions
This section provides a description of the special
bit types used in the Status and Control registers.
16-bit Register Word
Bit Number
FEDCBA9 8 7 6 5 4 3 2 1 0
10 Register Bits
Internal Address
(bits 0 - 5)
1 = Control/Configuration
0 = Status/Event
Suffix
CMD
CFG
CTL
Event
ST
74
Figure 23. Status and Control Register Format
Type
Read/Write
Read/Write
Read/Write
Read-only
Read-only
Read-only
Description
Comments
Command: Written once per frame to initiate transmit.
Configuration: Written at setup and used to determine
what frames will be transmitted and received and what
events will cause interrupts.
Control: Written at setup and used to determine what
frames will be transmitted and received and how the physi-
cal interface will be configured.
Event: Reports the status of transmitted and received
frames.
cleared when read
Status: Reports information about the configuration of the
CS89712.
Counters: Counts missed receive frames and collisions. cleared when read
Provides time domain for locating coax cable faults.
Table 34. Ethernet Port Register Types
DS502PP2
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