CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

Internal

Offset

# of

Bytes

0138

2

0140h

4

Initiate Transmit Registers

0144h

2

Type

RD

-

WR

0146h

2

WR

Description

Bus Status

Reserved

TxCMD (transmit

command)

TxLength (transmit length)

0148h

8

-

Reserved

Address Filter Registers

0150h

8

RW Logical Address Filter

(hash table)

0158h

6

RW Individual Address

015Eh

674

Frame Location

0400h

2

-

Reserved

RD RXStatus (receive status)

0402h

0404h

2

Read-only RxLength (receive length,

in bytes)

-

Read-only Receive Frame Location

0A00

-

Write-only Transmit Frame Location

Cross Reference

Note 2

Section 3.19, “Initiate Transmit Registers”,

Section 2.34, “Transmit Operation”

Section 3.19, “Initiate Transmit Registers”,

Section 2.34, “Transmit Operation”

Note 2

Section 3.20, “Address Filter Registers”,

Section 2.32.7, “Receive Ethernet Port

Locations”

Section 3.20, “Address Filter Registers”,

Section 2.32.7, “Receive Ethernet Port

Locations”

Note 2

Section 3.18, “Ethernet Port Status/Control

Registers”,

Section 2.32, “Basic Receive Operation”

Section 3.18, “Ethernet Port Status/Control

Registers”,

Section 2.32, “Basic Receive Operation”

Section 3.18, “Ethernet Port Status/Control

Registers”,

Section 2.32, “Basic Receive Operation”

Section 3.18, “Ethernet Port Status/Control

Registers”,

Section 2.34, “Transmit Operation”

Table 36. Ethernet Port 4 Kbyte Memory Register Address Map (Continued)

Notes: 1. All registers are accessed as 16-bit only.

2. Read operation from the reserved location provides undefined data. Writing to a reserved location or

undefined bits may result in unpredictable operation.

3.4 I/O Port Data Registers

3.4.1 PADR Port A Data Register (address 0x8000.0000)

Values written to this 8-bit read / write register will be output on Port A pins if the corresponding data direc-

tion bits are set high (port output). Values read from this register reflect the external state of Port A, not nec-

essarily the value written to it. All bits are cleared by a system reset.

3.4.2 PBDR Port B Data Register (address 0x8000.0001)

Values written to this 8-bit read / write register will be output on Port B pins if the corresponding data direc-

tion bits are set high (port output). Values read from this register reflect the external state of Port B, not nec-

essarily the value written to it. All bits are cleared by a system reset.

78

DS502PP2

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