CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

by the Ethernet port without software intervention.

All other event bits are cleared only by the software

reading the appropriate event register, either direct-

ly or through the Interrupt Status Queue (ISQ).

(RxDest and Rx128 can also be cleared by the soft-

ware reading the BufEvent register, either directly

or through the Interrupt Status Queue).

2.32.3.3 Acceptance Filtering

The third step of pre-processing is to determine

whether or not to accept the frame by comparing

the frame with the criteria programmed into the Rx-

CTL register. If the receive frame passes the Ac-

ceptance filter, the frame is buffered on chip. If the

frame fails the Acceptance filter, it is discarded.

The results of the Acceptance filter are reported in

the RxEvent register.

2.32.3.4 Normal Interrupt Generation

The final step of pre-processing is to generate any

enabled interrupts that are triggered by the incom-

ing frame. Interrupt generation occurs when the en-

tire frame has been buffered (up to the first

1518 bytes). For more information about interrupt

generation, see Section 2.31, “Managing Inter-

rupts & Status Queue”.

2.32.4 Buffering Held Receive Frames

If space is available, an incoming frame will be

temporarily stored in on-chip RAM, where it

awaits processing by the software. Although this

receive frame now occupies on-chip memory, the

Ethernet port does not commit the memory space to

it until one of the following two conditions is true:

1) The entire frame has been received and the soft-

ware has learned about the frame by reading the

RxEvent register, either directly or through the

ISQ.

or:

2) The frame has been partially received, causing

either the RxDest bit (BufEvent register bit F)

or the Rx128 bit (BufEvent register bit B) to be-

come set, and the software has learned about

the receive frame by reading the BufEvent reg-

ister, either directly or through the ISQ.

When the CS89712 commits buffer space to a par-

ticular held receive frame (termed a committed re-

ceived frame), no data from subsequent frames can

be written to that buffer space until the frame is

freed from commitment. (The committed received

frame may or may not have been received error

free.)

A received frame is freed from commitment by any

one of the following conditions:

1) The software reads the entire frame sequential-

ly in the order that it was received (first byte in,

first byte out).

or:

2) The software reads part or none of the frame,

and then issues a Skip command by setting the

Skip_1 bit (RxCFG register bit 6).

or:

3) The software reads part of the frame and then

reads the RxEvent register, either directly or

through the ISQ, and learns of another receive

frame. This condition is called an "implied

Skip". Ensure that the software does not do

“implied skips.”

Both early interrupts are disabled whenever there is

a committed receive frame waiting to be processed

by the software.

There are three possible ways that the software can

learn the status of a particular frame. It can:

1) Read the Interrupt Status Queue;

2) Read the RxEvent register directly ; or

3) Read the RxStatus register.

2.32.5 Receive Frame Visibility

Only one receive frame is visible to the software at

a time. The receive frame's status can be read from

DS502PP2

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