CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

responding register are cleared and the next report

in the queue moves to the front.

When the software starts reading the ISQ, it must

read and process all Event reports in the queue. A

read-out of a null word (0000h) indicates that all in-

terrupts have been read.

The ISQ is read as a 16-bit word. The lower six bits

(0 through 5) contain the register number (4, 8, C,

10, or 12). The upper ten bits (6 through F) contain

the register contents. The software must always

read the entire 16-bit word.

The active interrupt pin (INTRQx) is selected via

the Interrupt Number register (Ethernet Port offset

address 22h). As an additional option, all of the in-

terrupt pins can be 3-Stated using the same regis-

ters; see Section 3.17 for more details.

An event triggers an interrupt only when the En-

ableIRQ bit (17) of the Bus Control register is set.

After the CS89712 has generated an interrupt, the

first read of the ISQ makes the INTRQ output pin

go low (inactive). INTRQ remains low until the

null word (0000h) is read from the ISQ, or for

1.6µs, whichever is longer.

2.32 Basic Receive Operation

2.32.1 Overview

Once an incoming packet has passed through the

analog front end and Manchester decoder, it goes

through the following three-step receive process:

1) Pre-Processing

2) Temporary Buffering

3) Transfer to system RAM

As shown in the figure, all receive frames go

through the same pre-processing and temporary

buffering phases, regardless of transfer method

Once a frame has been pre-processed and buffered,

it can be accessed by the software.

2.32.2 Receive Configuration

After each reset, the CS89712 Ethernet port must

be configured for receive operation. This can be

done automatically using an attached EEPROM or

by writing configuration commands to the

CS89712’s internal registers (see Section 2.6,

“Ethernet EEPROM Configurations”). The items

that must be configured include:

• which types of frames to accept;

• which receive events cause interrupts; and,

2.32.2.1 Configuring the Physical Interface

Configuring the physical interface consists of en-

abling the receive logic for serial reception. This is

done via the LineCTL register. Bit 6 enables recep-

tion and bit E is used to reduce squelch.

2.32.2.2 Choosing Acceptable Frame Types

The RxCTL register selects which frame types will

be accepted by the Ethernet port. Bits 6 through E

of RxCTL are used for this. Refer to Section 2.32.7,

“Receive Ethernet Port Locations” for a detailed

description of Destination Address filtering, and

Section 3.18.4 on page 119 for RxCTL details.

2.32.2.3 Selecting Interrupt Events

The RxCFG and BufCFG registers are used to de-

termine which receive events will cause interrupts

to the processor. Bits 8, C, D and E of BufCFG are

used for this, and A, B, D and F of BufCFG. See

Section 3.18.2 and Section 3.18.8 for details. Note

that the DA filter must be passsed before there is an

interrupt.

2.32.3 Receive Frame Pre-Processing

The CS89712 pre-processes all receive frames us-

ing a four step process:

1) Destination Address filtering;

2) Early Interrupt Generation;

3) Acceptance filtering; and,

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DS502PP2

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