CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

If no link pulses are being received on the receiver,

the 10BASE-T transmitter is internally forced to an

inactive state unless bit DisableLT in the Test Con-

trol register is set to one.

2.28.3 Receiver

The 10BASE-T receive section consists of the re-

ceive filter, squelch circuit, polarity detection and

correction circuit, and link pulse detector.

2.28.3.1 10BASE-T Squelch Circuit

This circuit determines when valid data is present

on the RXD+/RXD- pair. Incoming signals passing

through the receive filter are tested by the squelch

circuit. Any signal with amplitude less than the

squelch threshold (either positive or negative, de-

pending on polarity) is rejected.

2.28.3.2 Extended Range

The CS89712 supports an Extended Range feature

that reduces the 10BASE-T receive squelch thresh-

old by approximately 6 dB. This allows the

CS89712 to operate with 10BASE-T cables that are

longer than 100 meters (100 meters is the maxi-

mum length specified by the Ethernet standard).

The exact additional distance depends on the qual-

ity of the cable and the amount of electromagnetic

noise in the surrounding environment. To activate

this feature, the software must set the LoRxSquelch

bit (LineCTL register bit E).

2.28.4 Link Pulse Detection

To prevent disruption of network operation due to

a faulty link segment, the Ethernet port continually

monitors the 10BASE-T receive pair (RXD+/

RXD-) for packets and link pulses. After each

packet or link pulse is received, an internal Link-

Loss timer is started. As long as a packet or link

pulse is received before the Link-Loss timer finish-

es (between 25 and 150 ms), the Ethernet port

maintains normal operation. If no receive activity is

detected, the Ethernet port disables packet trans-

mission to prevent "blind" transmissions onto the

network (link pulses are still sent while packet

transmission is disabled). To reactivate transmis-

sion, the receiver must detect a single packet (the

packet itself is ignored), or two link pulses separat-

ed by more than 2 to 7 ms and no more than 25 to

150 ms (see the Characteristics / Specifications

section for 10BASE-T timing).

The state of the link segment is reported in the

LinkOK bit (LineST register bit 7). If the HC0E bit

(SelfCTL register bit D) is clear, it is also indicated

by the LINKLED output pin. If the link is "good",

the LinkOK bit is set and the LINKLED pin is driv-

en low. If the link is "bad" the LinkOK bit is clear

and the LINKLED pin is high. To disable this fea-

ture, the DisableLT bit (TestCTL register bit 7)

must be set. If DisableLT is set, the Ethernet port

will transmit and receive packets independent of

the link segment.

2.28.5 Receive Polarity Detection/Correction

The Ethernet port checks the polarity of the receive

half of the twisted pair cable. If the polarity is cor-

rect, the PolarityOK bit (LineST register bit C) is

set. If the polarity is reversed, the PolarityOK bit is

clear. If the PolarityDis bit (LineCTL register bit

C) is clear, the Ethernet port automatically corrects

a reversal. If the PolarityDis bit is set, the port does

not correct a reversal. The PolarityOK bit and the

PolarityDis bit are independent.

To detect a reversed pair, the receiver examines re-

ceived link pulses and the End-of-Frame (EOF) se-

quence of incoming packets. If it detects at least

one reversed link pulse and at least four frames in a

row with negative polarity after the EOF, the re-

ceive pair is considered reversed. Data received be-

fore the correction of the reversal is ignored.

2.28.6 Collision Detection

If half-duplex operation is selected (FDX bit E is

clear), the Ethernet port detects a 10BASE-T colli-

sion whenever the receiver and transmitter are ac-

tive simultaneously. When a collision is present,

54

DS502PP2

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