CS89712-CB View Datasheet(PDF) - Cirrus Logic
Part Name
Description
MFG CO.
CS89712-CB Datasheet PDF : 170 Pages
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CS89712
4. TEST & DEBUG MODES
The CS89712 supports a number of hardware acti-
vated test and debug modes.
4.1 Entering test modes
Test modes are activated by the pin combinations
shown in Table 85. All latched signals will only al-
ter test modes while NPOR is low, their state is
latched on the rising edge of NPOR. This allows
these signals to be used normally during various
test modes.
Within each test mode, a selection of pins is used as
multiplexed outputs or inputs to provide / monitor
the test signals unique to that mode.
4.1.1 Oscillator and PLL Bypass Mode
This mode is selected by nTEST[0] = 1 and
nTEST[1] = 0.
In this mode, all the internal oscillators and PLL are
disabled, and the appropriate crystal oscillator pins
become the direct external oscillator inputs bypass-
ing the oscillator and PLL. MOSCIN must be driv-
en by a 36.864 MHz clock source and RTCIN by a
32.768 kHz source.
4.1.2 Oscillator and PLL Test Mode
This mode is selected by nTEST[0] = 0,
nTEST[1] = 1, Latched nURESET = 0
This test mode will enable the main oscillator and
will output various buffered clock and test signals
derived from the main oscillator, PLL, and 32-kHz
oscillator. All internal logic in the CS89712 will be
static and isolated from the oscillators, with the ex-
ception of the 6-bit ripple counter used to generate
576 kHz and the Real-Time Clock divide chain.
Port A is used to drive the inputs of the PLL direct-
ly, and the various clock and PLL outputs are mon-
itored on the COL pins. Table 86 defines the
CS89712 signal pins used in this test mode. This
mode is only intended to allow test of the oscilla-
tors and PLL. Note that these inputs are inverted
before being passed to the PLL to ensure that the
default state of the port (all zero) maps onto the cor-
rect default state of the PLL (TSEL = 1, XTALON
= 1, PLLON = 1, D0 = 0, D1 = 1, PLLBP = 0). This
state will produce the correct frequencies as shown
in Table 86. Any other combinations are for testing
the oscillator and PLL and should not be used in-
circuit.
Test Mode
Normal operation
(32-bit boot)
Normal operation
(8-bit boot)
Normal operation
(16-bit boot)
Alternative test ROM
boot
Oscillator / PLL bypass
Oscillator / PLL test
mode
ICE Mode
System test (all HiZ)
Latched
nMEDCHG
1
1
1
0
X
X
X
X
Latched
PE[0]
0
1
0
X
X
X
X
X
Latched
PE[1]
0
Latched
nURESET
X
0
X
1
X
X
X
X
X
X
0
X
1
X
0
Table 85. CS89712 Hardware Test Modes
nTEST[0]
1
1
1
1
1
0
0
0
nTEST[1]
1
1
1
1
0
1
0
0
136
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