CS89712
3.18.16 Ethernet IRQ Control Register (BusCTL, address offset 116h)
7
6
5:0
F
E
D:8
RSVD
010111
EnableIRQ
RSVD
Bit
5:0
6
D:8
F
Description
010111: These bits provide an internal address used by the CS89712 to identify this as register
17, the Bus Control Register.
RSVD: Reserved; must be a “0” when writing to this register.
EnableIRQ: When set, the CS89712 will generate an interrupt in response to an interrupt event
(Section 2.31, “Managing Interrupts & Status Queue”). When cleared, the CS89712 will not
generate any interrupts.
Table 81. Ethernet IRQ Control
After reset, if no EEPROM is found by the CS89712, then the register has the following initial state. If an EEPROM
is found, then the register’s initial value may be set by the EEPROM. See Section 2.24, “Programming the EE-
PROM”.
Reset value is: 0000 0000 0001 0111
DS502PP2
131