CS89712-CB View Datasheet(PDF) - Cirrus Logic

Part Name

Description

MFG CO.

CS89712-CB

High-Performance, Low-Power System-on-Chip with 10BASE-T Ethernet Controller

Cirrus Logic 

CS89712

3.18.17 TX Bid Status Register (BusST, address offset 138h)

7

6

TxBidErr

C

B

5:0

011000

A

F

E

D

9

8

Rdy4Tx NOW

BusST describes the status of the current transmit operation.

Bit

5:0

7

Description

011000: These bits provide an internal address used by the CS89712 to identify this as register

18, the Bus Status Register. When reading this register, these bits will be 011000, where the

LSB corresponds to Bit 0.

TxBidErr: If set, the software has commanded the Ethernet port to transmit a frame that the

Ethernet port will not send. Frames that the Ethernet port will not send are:

1) Any frame greater than 1514 bytes, provided that InhibitCRC

(Register 9, TxCMD, Bit C) is clear.

2) Any frame greater than 1518 bytes.

Note that this bit is not set when transmit frames are too short.

8

Rdy4TxNOW: Rdy4TxNOW signals the software that the Ethernet port is ready to accept a

frame from the software for transmission. This bit is similar to Rdy4Tx (Register C, BufEvent,

Bit 8) except that there is no interrupt associated with Rdy4TxNOW. The software can poll the

CS89712 and check Rdy4TxNOW to determine if the CS89712 is ready for transmit. (See Sec-

tion 2.34, “Transmit Operation” for a description of the transmit bid process.)

Table 82. TX Bid Status

Reset value is: 0000 0000 0001 1000

132

DS502PP2

Share Link: